Xtensa Xplorer Integrated Design Environment (IDE)

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Everything You Need to Build High-Performance DPUs

Tensilica's Processor Developer's Toolkit contains all the tools necessary to create and analyze extremely high-performance application-specific Xtensa DPUs.

Tensilica’s Xtensa Xplorer GUI serves as the cockpit for the entire design experience. From Xtensa Xplorer, you can profile your application code, identify “hot spots" that can benefit from acceleration, and make the changes necessary to speed up that code. Using a check-box menu within the GUI, you can configure processors to include features you need and remove features you don’t – options for processor interface, memories, operating system support, EDA scripts, debug and trace, and much more.

Xplorer flow

Xtensa Xplorer serves as the cockpit for custom processor development

See How Easy It Is to Configure an Xtensa Processor

See our CTO, Chris Rowen, explain the process of configuring a processor. Find out more about all of our configuration options.. Using a check-box menu within the GUI, you can configure processors to include features you need and remove features you don't - options for processor interface, memories, operating system support, EDA scripts, debug and trace, and much more are supported.

Use TIE to Add Custom Instructions

Tensilica's TIE language is similar to Verilog and simplifies your ability to add optimizing custom instructions to Xtensa processors.  By modifying the Xtensa processor, Tensilica's customers often get 10 to 100 times (or more) better performance and lower power when compared to alternative processor architectures, allowing Xtensa processors to be used in critical dataplane SOC functions where previously standard microprocessors or DSPs could not deliver the needed performance, throughput or low-power; and hand-coded RTL hardware blocks had to be used.

Tensilica's TIE Compiler automatically creates updates to the entire Xtensa toolchain including the ISS and SystemC models, in minutes on your desktop.

Profile, Compare and Save Configurations

You can profile, compare and save many different processor configurations, so you can pick the right one for your application. Also, you can model and simulate multiple-processor subsystems in this environment using Tensilica's Xtensa Modeling Protocol (XTMP) or Xtensa SystemC Modeling Protocol (XTSC).

For integration into the dataplane with custom logic, Tensilica's Xtensa SystemC (XTSC) can be used for simulation of DPUs with SystemC Transaction Level Modeling (TLM) hardware. Co-simulation with RTL level blocks and the Xtensa ISS is possible using Pin Level XTSC. This offers a pin-level, cycle-accurate modeling of Xtensa DPU interfaces for use in Verilog simulations.

Processor Generation

Xtensa Xplorer serves as the gateway to the Xtensa Processor Generator. Once a processor configuration is finalized, the Xtensa Processor Generator creates the automatically verified Xtensa processor to match all of the configuration options and extensions you have defined, in about an hour. The full software tool chain is also created, matching all processor modifications you have made.

Pipeline Viewer

Xtensa Xplorer includes a sophisticated Pipeline Viewer that helps you visualize the performance impact of designer-defined instructions, without the need to become a processor pipeline expert. In one quick step, Xtensa Xplorer's Pipeline Viewer will illustrate the impact of an instruction on the execution pipeline, providing instant feedback on the efficiency of a proposed new instruction and helping you tune the source TIE for optimal implementation.

Pipeline Viewer shows instructin flow of disassembled code.

Analyze and Iterate

Xtensa Xplorer not only provides the tools to quickly develop optimized processors and simulate systems of processors, but also provides the tools that enable you to visualize and analyze simulation results, tune system or processor configurations, and rapidly compare alternative implementations.

The TIE Analyzer estimates gate count and silicon area for new instructions

This allows Xtensa DPUs to be used in critical SOC functions where previously standard microprocessors or DSPs could not deliver the needed performance, throughput or low-power; and hand-coded RTL hardware blocks had to be used. And this allows Xtensa processors to be used by designers with no previous processor design experience.

Performance charts visually compare different configurations.

You can profile, compare and save many different processor configurations, so you can pick the right one for your application. Also, you can model and simulate multiple processor subsystems in this environment using Tensilica’s XTensa Modeling Protocol (XTMP) and XTensa SystemC (XTSC) modeling environment.

Visualize and Analyze: Rapid Iteration of Complex SOC Architectures

Xtensa Xplorer not only provides the tools to quickly develop optimized processors and simulate systems of processors, but also provides the tools that enable you to visualize and analyze simulation results, tune system or processor configurations, and rapidly compare alternative implementations.

Project Management and Source Code Editing in Xtensa Xplorer

The Xtensa Xplorer IDE builds on the Eclipse project management and revision control mechanisms. The Xplorer IDE automatically creates and manages project and library builds and makefiles. The designer can set the various tool options and flags (example: compiler, assembler and linker flags) using the build properties dialog window. Multiple build properties can be set depending on whether the target is to build a debug version or optimized version of the application binary. Optionally, designers can create unmanaged projects that allow total designer control over build target properties.

The C/C++ source code editor allows designers to efficiently create and modify their code using rich editing and indexing capabilities. The editor uses syntax highlighting of language features such as keywords, comments, declarations, and strings to enable rapid software development and debugging. Symbol indexing allows program navigation including find declaration, find definition, and find type. Other features in the editor that speed up coding include code completion, auto indenting, and quick diff. Block comment/uncomment is useful when debugging or profiling large source files. Designers can choose other views, such as source outline, make target, and problems.

The rest of the software development tool chain (linker, assembler, debugger) is based on standard GNU tools. Since these tools and the XCC compiler front-end use the same preprocessor as in the GNU tools, the flags for the C/C++ preprocessor remain the same. The assembler and linker also utilize the same flags as the GNU versions of the tools.

Xtensa Debugger

The debugger allows you to target the pipeline/cycle accurate ISS, Tensilica’s TurboXim fast functional simulator, or an external probe to a hardware development board. The GUI-based debugger allows full system visibility into your project; it controls program execution (i.e., C instruction and assembly instruction stepping, stepping into or over functions) and provides views to variables, breakpoints, memory, registers, etc,. The debugger also displays registers and internal wires defined by the designer in TIE instructions. Source and assembly code can be made visible simultaneously while debugging an application and either code window can be single stepped. The debugger interoperates seamlessly with the other development tools (compiler tool chain, instruction set simulator) to allow rapid code development for Xtensa processor systems.

Gateway to Xtensa Processor Generator

Xtensa Xplorer serves as the gateway to the Xtensa Processor Generator. Once a processor configuration is finalized, the Xtensa Processor Generator creates the automatically verified Xtensa processor to match all of the configuration options and extensions you have defined, in less than an hour. A software tool chain is also created matching all processor modifications you have made.

Multiple Processor Design

Xplorer, while extremely useful for designs with only one Xtensa processor, is ideally targeted to multiple-processor SOC (MPSOC) designs. It facilitates MPSOC development with tools for build management; profiling; batch building; system memory map assignment; and integrated multiple-processor simulation, creation, and debugging using Tensilica’s Xtensa Modeling Protocol (XTMP).

ECLIPSE Platform

The Xtensa Xplorer IDE is based in part on the open-source ECLIPSE platform for tool integration. More information on the ECLIPSE partnership can be found at www.eclipse.org.

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