TIE Compiler

Product Briefs

Xtensa Processor Developer's Toolkit Product Brief

Xtensa Software Developer's Toolkit Product Brief

White Papers

TIE - The Fast Path to High-Performance Embedded SOC Processing

Optimize SOC Performance Using Memory Tuning and System Simulation

Avoid Bus Bottlenecks and Get More Performance from your ASIC and SOC Designs by Using High-Speed On-Chip I/O

More white papers...

The Real Power of Tensilica's Processors - TIE

The TIE language offers a wide range of flexibility in adding multi-cycle, pipelined execution units, register files, state registers, SIMD arithmetic and logic units, creating wide (up to 512-bit) Load/Store instructions, and adding designer-defined I/O Ports, Queues, and Lookups. While TIE can be used with both Xtensa 9 and Xtensa LX4, you can use it for more functions - such as a second Load/Store unit or FLIX (flexible length instruction extensions with the more powerful Xtensa LX4. See this page for a description of the major differences between the two processors.

Tensilica has a number of automated tools that will help you create your TIE instructions. Tensilica offers a Flexible Length Instruction eXtension (FLIX) generator for VLIW accelerations and a Manual Fusion Editor to help designers create chains or fusions of fundamental computation operations to improve performance.

The TIE Compiler

While you can select from a large number of check-box configuration options, the real power of Tensilica's Xtensa design environment comes from the use of TIE. TIE "bridges the gap" between the software and hardware design realms, as it is a hybrid of C and Verilog and very easy to learn. TIE lets you add new processor functionality in the form of instructions, execution units, wide load-store instructions, designer-defined I/O interfaces, and designer-defined register files and state registers - all without the need to modify (and then verify) the processor RTL.

The TIE Compiler is a tool that you use during the development of custom processor hardware extensions.  The TIE Compiler also updates the compiler tool chain (XCC compiler, assembler, debugger, profiler) and the simulation models (instruction set simulator and the XTMP, XTSC and pin-level XTSC system modeling environment) so they understand and fully utilize these new functions.

You use the TIE Compiler on your local workstation/PC to iterate in minutes to determine the best instructions for the performance you need combined with any area and power considerations. Once you've determined the optimal TIE instructions for your application, that TIE file becomes input for the Xtensa Processor Generator.  The Processor Generator automatically produces the entire processor RTL, including the base processor with all configuration options and all TIE extensions.

The TIE editor simplifies new instruction development