Develop Configurations

Product Briefs

Xtensa Processor Developer's Toolkit Product Brief

Xtensa Software Developer's Toolkit Product Brief

White Papers

TIE - The Fast Path to High-Performance Embedded SOC Processing

Optimize SOC Performance Using Memory Tuning and System Simulation

Avoid Bus Bottlenecks and Get More Performance from your ASIC and SOC Designs by Using High-Speed On-Chip I/O

More white papers...

Use Xtensa Xplorer to Compare Trade-offs, Get Gate Count Estimates

Xtensa Xplorer serves as the cockpit for basic design management, invocation of Tensilica processor configuration tools (, Xtensa Processor Generator, TIE Compiler) and software development tools (Xtensa C/C++ Compiler, Xtensa Instruction Set Simulator).

Xtensa Xplorer dramatically accelerates the processor optimization cycle by providing an automated, visual means of profiling and comparing different processor configurations. Since it only takes an hour for the Xtensa Processor Generator to create a new, customized version once the designer configures the processor and creates the instruction extensions, customers will want to try many different options.

Designers can use the , which integrates into the Xtensa Xplorer design envirnoment, to analyze C/C++ code and automatically generate TIE instructions to modify the Xtensa LX processor. Also, TIE instructions for any Tensilica processor can be generated manually by the design team.

Xtensa Xplorer includes an interactive TIE editor that lets designers get immediate feedback into designer-defined TIE instructions. For example, a screen from the interactive TIE editor is shown below.

Designers can get insight into the gate-count size of their TIE instructions by looking at this screen:

Gate-count estimates are provided per instruction for each register file or user state. This can quickly let designers make intelligent trade-offs between area (gate count) and performance increases with extra TIE instructions.

Xtensa Xplorer includes a sophisticated Pipeline Viewer that helps the designer visualize the performance impact of designer-defined instructions, without the need to become a "processor pipeline expert." In one quick step, Xplorer's Pipeline Viewer illustrates the impact of an instruction on the execution pipeline, providing instant feedback on the efficacy of a proposed new instruction and helping the designer tune the source TIE for optimal implementation.

Pipeline Viewer shows instruction flow of disassembled code.