Xtensa Processor Developer's Toolkit Product Brief
Xtensa Software Developer's Toolkit Product Brief
Diamond Software Tools Product Brief
Processor Core Customization: Your SOC design team's fastest route from C to gates
Boost ASIC and SOC Performance by Matching Processor to Task through Automated Processor Generation
How to Minimize Energy Consumption while Maximizing ASIC and SOC Performance
Tensilica delivers patented, proven tools that automate the process of generating a custom processor along with matching software tools. This is our eighth generation of these tools, which have been proven in hundreds of designs. Whether your design is for a simple controller or a complex multi-core DSP design, Tensilica has the tools you need to create successful products.
If you've looked at Tensilica's Internet site or processor product briefs, you know that you can extend Tensilica's Xtensa dataplane processors (DPUs) - adding instruction sets, execution units, processor I/O interfaces - to exactly match your application needs.
By customizing the processor for a particular application you can often get significantly lower energy consumption and 10-100x performance increases. This level of performance and efficiency is often essential in the SOC dataplane.
By customizing the processor, you also create a core that's uniquely yours. This gives you extra protection in today's highly competitive marketplace.
The Xtensa Processor Developer's Toolkit is the integrated design environment that delivers powerful tools to your desktop that guide you through the processor customization process. You'll find that Tensilica has created the most advanced, powerful and easy-to-use tools for processor customization.
The Processor Developer's Toolkit is required for any design team that is using Tensilica's TIE (Tensilica Instruction Extension) instructions to modify the processor. If you are using an Xtensa processor with no modification or only changes to configuration options, you do not need the Processor Developer's Toolkit - you'll only need the Software Developer's Toolkit (see separate product brief).
Configurability of a Tensilica processor core never compromises the underlying base Xtensa instruction set, thereby ensuring availability of a robust ecosystem of third party application software and development tools. All configurable, extensible Xtensa processors are always compatible with major operating systems, debug probes and ICE solutions; and always come with an automatically generated, complete software development toolchain including an advanced integrated development environment based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry-standard GNU toolchain.
Tensilica’s Xtensa Xplorer GUI serves as the cockpit for the entire design experience. From Xtensa Xplorer, you can profile your application code, identify “hot spots" that can benefit from acceleration, and make the changes necessary to speed up that code. Using a check-box menu within the GUI, you can configure processors to include features you need and remove features you don’t – options for processor interface, memories, operating system support, EDA scripts, debug and trace, and much more.
See our CTO, Chris Rowen, explaining processor configuration. Find out more about configuring a processor in this section.
You can quickly extend the processor’s instruction set by adding new instructions using the Tensilica Instruction Extension (TIE) language, a hybrid of C and Verilog, which is the easiest-to-use method for saving power, increasing performance, and reducing clock frequency. By modifying the Xtensa processor, Tensilica’s customers often get 10 to 100 times (or more) better performance and lower power when compared to alternative processor architectures.
This allows Xtensa processors to be used in critical SOC functions where previously standard microprocessors or DSPs could not deliver the needed performance, throughput or low-power; and hand-coded RTL hardware blocks had to be used.
Tensilica’s TIE Compiler automatically creates updates to the entire Xtensa toolchain including the ISS and SystemC models, in minutes on your desktop. From Xtensa Xplorer, you can invoke Tensilica’s XPRES Compiler, which analyzes C/C++ application code and automatically creates TIE code for Tensilica’s Xtensa processors that will significantly speed up that application. This often gives you the performance boost you need without the need to figure out the necessary processor extensions yourself.
You can profile, compare and save many different processor configurations, so you can pick the right one for your application. You can use the ISS or TurboXim for simulations. Also, you can model and simulate multiple processor subsystems in this environment using Tensilica’s Xtensa Modeling Protocol (XTMP) or Tensilica's XTensa SystemC (XTSC) modeling .
Xtensa Xplorer serves as the gateway to the Xtensa Processor Generator. Once a processor configuration is finalized, the Xtensa Processor Generator creates the automatically verified Xtensa processor to match all of the configuration options and extensions you have defined, in less than an hour. A software tool chain is also created matching all processor modifications you have made.
Find out more about the Xtensa Processor Developer's Toolkit on the following pages:
Find out how you can:
