ConnX DPUs

Products » Comms DSP » ConnX DPUs

Tensilica Baseband Dataplane Processors

Dataplane processors

Tensilica's Range of Dataplane Processors

Tensilica's underlying Xtensa processor technology allows the creation of customized processor cores that can be optimized for specific functions.No other companies let you customize features like Tensilica does. You can make Xtensa processors uniquely your own in two basic ways:

  • Configurability - designers are offered a menu of checkbox and drop-down menu options so they can pick just the features they need - including multiple pre-verified DSP engines
  • Extensibility - designers can add their own instructions, registers, register files, and much more using the Tensilica Instruction Extension (TIE) methodology. The designer only has to specify the functional behavior of the new data path elements in the TIE language (Verilog-like) and then the RTL and whole tool chain is automatically generated.

We Make Customization Easy

Our automated tools help you make intelligent decisions about what to change - and what not to change - in your design to get the performance improvements and low power you need. You can test out changes easily and immediately see the results. No guessing required.

When you've figured out the best implementation, our automated Xtensa Processor Generator creates, in a matter of minutes, pre-verified RTL and a complete software toolchain, including EDA scripts for production.

Accelerate Hot Spots in Applications

You don't have to go to higher MHz to get higher performance. By adding instructions in our Verilog-like language (TIE), you can accelerate hot spots in your applications. You can pump data through our cores with up to two  512-bit-wide data load/stores per cycle, or bypass the bus entirely with our unique GPIO and FIFO Queues. Here are some ways you can customize our DPUs:

Data paths

  • The width of data load/store, computation execution and register files can all be tailored to specific application

SIMD widths

  • Some application may greatly benefit from vectorizing computation through a SIMD machine
  • The size of SIMD and vector "strides" can be customized to optimum performance per power/area for the application

Custom instructions

  • Create instructions that perform application specific tasks
  • Create 'incredible performance' for application, reduce instruction memory footprint

Parallel instruction execution

  • VLIW architecture to enable parallel computation of instructions
  • Example: use one instruction to perform load, execute, store

See our Xtensa Processor section for more details.

Tensilica-Generated DPUs for Baseband

Tensilica has used this technology to build optimized DPUs for baseband applications. These DPUs, coupled with the ConnX DSP cores, have laid the foundation for OSO developers to implement LTE and  LTE-Advanced basestations and user equipment. These include:

  • ConnX BSP3 DPU - an optimized bit stream processor for multi-standard wireless baseband phy
  • ConnX SSP16 DPU - a 16-way soft stream processor for multi-standard baseband phy
  • ConnX Turbo16MS DPU - a multi-stanard turbo decoder

Generate Your Own DPU

Area of LTE-Advanced computation that may well lend themselves to offloading and acceleration with a customized DPU are:

  • Large FFT computation (greater than 1K point), parallel processing of FFT computation
  • Parallel processing of 32-tap FIRs
  • Matrix calculations
  • 3G Despread functionality
  • MIMO ML decoder function
  • Viterbi functionality

Marketing Agency