Software and Tool Support

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The Tools and Software You Need to be Successful

Tensilica's ConnX D2 DSP engine is a new architecture, designed from the start to give the best performance with small size and a modern, efficient optimizing compiler. While our architecture is new, because we've optimized the ConnX D2 DSP's compiler to efficiently handle the C language plus many popular intrinsic functions, there's a large base of software that will run, no modifications required.

Existing DSP Code Base Support

The ConnX D2 DSP engine includes support for TI C6x C-intrinsics and ITU C-intrinsics. Compiling an application written with TI or ITU C intrinsics merely requires inclusion of a C header file that maps these intrinsics to ConnX D2 instructions. This means that existing code bases (TI or ITU) can be ported quickly to the ConnX D2 DSP engine.

Both the ITU and TI C6x instrincs are mapped in most cases to a single instruction in the ConnX D2 instruction set, providing for the most efficient execution of the intrinsics. A good example of this is the ITU "mult_r" instrinsic, which is implemented in one MAC-with-rounding instruction of the ConnX D2 ISA.

Tool Support for Processor Designers

Every Xtensa LX processor with (or without) the ConnX D2 DSP Engine is automatically generated with a complete set of software development and modeling tools tailored to the exact Xtensa LX configuration.

Tensilica's Xtensa Xplorer GUI serves as the cockpit for the entire design experience. From Xtensa Xplorer, designers can profile their application code, identify "hot spots" that can benefit from acceleration, and make the changes necessary to speed up that code. Using a check-box menu within the GUI, designers can configure processors to include the ConnX D2 DSP Engine and other features they need including options for processor interface, memories, operating system support, EDA scripts, debug and trace, and much more.

Designers can quickly extend the processor's instruction set by adding new instructions using the Tensilica Instruction Extension (TIE) language, a hybrid of C and Verilog, which is the easiest-to-use method for saving power, increasing performance, and reducing clock frequency.

Designers can profile, compare and save many different processor configurations, so they can pick the right one for their application. The ISS or TurboXim can be used for simulations. Also, designers can model and simulate multiple processor subsystems in this environment using Tensilica's XTensa Modeling Protocol (XTMP) or Xtensa SystemC (XTSC) modeling.

Xtensa Xplorer serves as the gateway to the Xtensa Processor Generator. Once a processor configuration is finalized, the Xtensa Processor Generator creates the automatically verified Xtensa processor to match all of the configuration options and extensions required in less than an hour. A software tool chain is also created matching all processor modifications that have been made.

Tool Support for Software Developers

The Xtensa Software Developers Toolkit (SDK) provides a comprehensive collection of code generation and analysis tools that speed the software application development process. Tensilica's Eclipse-based Xtensa Xplorer graphical user interface (GUI) serves as the cockpit for the entire development experience and also provides powerful visualization tools to aid application optimization.

The entire Xtensa software development tool chain (the compiler, linker, assembler, debugger, instruction set simulator, etc.), along with simulation models, RTOS ports, optimized C-libraries, etc., are automatically configured for the tailored processor hardware.

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