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Advanced Instruction Set
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Optimizing a DSP Architecture for Wireless Baseband
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Analyst Reports
Tensilica DSP Targets LTE Advanced - Microprocessor Report review of ConnX BBE64
Tensilica Plays Baseband - New ConnX Core Aims for Low-Power Wireless Communications - Microprocessor Report review of ConnX BBE16
Tensilica Xtensa LX Processor with Vectra LX - BDTI
An Instruction Set Optimized for Communications Applications
The ConnX BBE16 DSP engine is an optional element of the popular Xtensa architecture that implements a rich set of generic instructions optimized for efficient embedded processing. The power of the ConnX BBE16 comes from a comprehensive DSP and baseband instruction set, for a total of over 500 instructions.
A wide variety of load/store operations supports six different addressing modes with support for 16b/32b scalar and vector data types. Unaligned load/stores with masking deliver full bandwidth loads and stores for unaligned data. Vector data management is supported with data packing and shifting.
Multiply operations include complex and scalar 18bx18b multiply, multiply-round, multiply-add and multiply subtract functions. Complex-number functions include support for conjugate arithmetic and magnitude operations as well as full precision arithmetic and saturated/rounded outputs. The ConnX BBE16 is capable of performing up to 16 multiplies per operation. BBE16 includes extended precision with guard bits on all register data and full support of double precision data, 40-bit accumulation on all MAC operations without performance penalty. A wide variety of arithmetic, logical and shift operations are supported for up to eight data words per cycle. There is full support for matrix multiplication with acceleration for OFDM matrix operations.
The ConnX BBE16 directly supports single cycle radix-4 and radix-8 butterfly operations enabling efficient high-speed FFT implementations. Support for a single cycle 4-tap FIR filter with complex taps and single cycle 16-tap FIR filter with real taps allows efficient filtering operations. Special instructions supporting radix 3 / 5 FFT are also provided. Symmetric filters on real and complex data at double rate, eg. 32 real taps/cycle.
For further application acceleration optional instruction packages are available for 8-way SIMD integer and fractional divide, 4-way SIMD reciprocal square root and de-spreading functions (16 complex MACs/cycle).
The ConnX BBE16 is code compatible with Tensilica's broad ConnX DSP product line.
Extensibility
In order to support connectivity to a wide variety of coprocessors, the underlying Xtensa platform supports custom ports (general purpose wire interfaces) and queue (FIFO) interfaces. These custom interfaces can be defined to match the interfaces of existing RTL hardware blocks without the need to redesign those blocks. Buffered communication between two ConnX BBE16s or between a ConnX BBE16 and an RTL block can be automatically implemented using queue interfaces and fully supported in programming and modeling tools.
Local memories can be connected directly to a ConnX BBE16 DSP using the Lookup interface that allows accessing such memories without needing to use the load and store instructions on the processor memory bus. This allows efficient implementation of functions that require storage of multiple intermediate datasets. The ConnX BBE16 also can be modified and extended by defining new instructions, registers, and execution units to augment the existing instruction set.
