ConnX D2 DSP Engine

ConnX D2 Named in Top 100 list by EDN editors in DSP category

Product Briefs

ConnX D2 Product Brief

ConnX Baseband Engine Product Brief

ConnX Atlas LTE Reference Architecture Product Brief

545CK Product Brief

Xtensa LX2 with Vectra Product Brief

HiFi 2 Audio DSP Product Brief

388VDO Video DSP Product Brief

White Papers

Cut DSP Development Time - Get High Performance From C, No Assembly Required

Optimizing a DSP Architecture for Wireless Baseband

A Designers Guide to HD Video Pre- and Post-Processing

Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC

See our complete white paper library

Presentations

The Five Pitfalls of 4G Baseband SOC Design

Everything You Wanted to Know About Video Processing - but Were Afraid to See

Everything You Wanted to Know About Blu-ray Audio - but were Afraid to Hear

Application Notes

Turbo Coding on Xtensa Processors

Implementing the Fast Fourier Transform (FFT)

See our complete application note library

Analyst Reports

Tensilica Plays Baseband - New ConnX Core Aims for Low-Power Wireless Communications - Microprocessor Report

Tensilica Xtensa LX Processor with Vectra LX - BDTI

Why We Need a New DSP for SOC Designs

See our new ConnX D2 White Paper

The rapid changes in wireline and wireless communications, disk drives, home entertainment devices, and computer peripherals are driving demand for 16-bit fixed-point DSPs. Stand-alone DSP chips are no longer cost effective for most of these price-sensitive applications. Instead, there's growing demand for general-purpose 16-bit DSP engines that can be easily designed into highly integrated system-on-chip (SOC) silicon.

At the same time, the growth of multiple standards and the complexity of these standards is driving developers away from traditional assembly-code programmed DSPs towards integrated architectures that combine excellent DSP performance with generalized high performance when developing with compiled native C control code.

The market needs a DSP engine that can easily be customized if necessary, integrated into a SOC design, and programmed most often in C, rather than assembly code. This will help speed new products to market as quickly as possible.

ConnX D2 DSP Engine

The ConnX D2 DSP engine is a click-box option for Tensilica's benchmark-breaking Xtensa LX processor technology. The ConnX D2 option adds dual 16-bit multiply-accumulate (MAC) units and a 40-bit register file to the base RISC architecture of the Xtensa LX processor. The ConnX D2 engine utilizes two-way SIMD (single instruction, multiple data) instructions to provide high performance on vectorizable C code. It also delivers dual-MAC performance using 64-bit VLIW (very long instruction word) instructions for code that cannot be vectorized.

The ConnX D2 DSP engine delivers outstanding 16-bit fixed point "out of the box" performance on compiled C code, without the need for assembly code optimization. This allows SOC development teams to have greater flexibility in resource allocation as well as the ability to quickly change algorithms. C code optimized with TI C6x or ITU C intrinsic functions compiles directly to the ConnX D2 instruction set, allowing developers to benefit from pre-existing TI and ITU code bases.

The ConnX D2 engine is supported by the comprehensive Eclipse-based Xtensa Xplorer software development environment containing everything from a source code editor, debugger, and ISS to the highly optimized Xtensa C/C++ (XCC) compiler that provides excellent code density.

ConnX D2 Features

• Both SIMD and 2-way FLIX (parallel VLIW) operations
• Optimized, vectorizing XCC Compiler
• High-performance DSP instruction set
• Dual write ports compute up to three results/cycle
• Supports TI (C6x) and ITU-T C intrinsic code base
• Bit-for-bit compatible with TI C6X code
• C-centric programming model supports standard C 16-bit, 32-bit and 40-bit data types

ConnX D2 Benefits

• Outstanding "out of the box" performance on compiled C source
• Reduces or eliminates the need for assembly code
• Performance acceleration for vectorizable code
• VLIW parallel execution for non-vectorizable code
• Large base of pre-optimized C code
• Quick and easy compiling of C code optimized with TI C6x intrinsics
• Quickly leverage all ITU-T reference code using ITU C intrinsics

The Flexibility of C Programming with Assembly Level Performance

The ConnX D2 DSP Engine, used with Tensilica's Xtensa LX processor core, provides approximately 20% higher performance than conventional dual-MAC architectures.

Small size: Total core size less than 70,000 gates or 0.18mm² in 65nm GP, after full place-and-route, when optimized for area/power.

Low power: 52 µW/MHz in 65nm GP running AMR-NB (VAD2) algorithm.

High performance: 600 Mhz in 65nm GP after full place-and-route, when optimized for speed.

Complete with Reference Cores

We've put together two reference configurations of the Xtensa LX with ConnX D2. These reference cores are available within the Xtensa Xplorer tool suite, letting you get up and running in a very short time. Here are the specifications for these two reference cores in 65nm GP process technology: