Products
System Design with the ConnX Baseband Engine
Product Briefs
HiFi 2 Audio DSP Product Brief
White Papers
Cut DSP Development Time - Get High Performance From C, No Assembly Required
Optimizing a DSP Architecture for Wireless Baseband
A Designers Guide to HD Video Pre- and Post-Processing
Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC
See our complete white paper library
Analyst Reports
Tensilica DSP Targets LTE Advanced - Microprocessor Report review of ConnX BBE64
Tensilica Plays Baseband - New ConnX Core Aims for Low-Power Wireless Communications - Microprocessor Report review of ConnX BBE16
Tensilica Xtensa LX Processor with Vectra LX - BDTI
Designing in One to Eight ConnX Baseband Engines
The architecture of the ConnX Baseband Engine is designed to stand alone or in groups of 2, 4 or 8 depending on system requirements.
Single DSP System
The Connx Baseband Engine supports easy system design into typical system architectures. It's high-bandwidth processor interface directly supports a range of standard bus bridges, including the popular AMBA bridge.
The processor interface and tightly coupled memories support a bus-based DMA controller to hide memory latency.
Because the ConnX Baseband Engine is fully configurable, it provides support for multi-core communications and DSP-RTL integration as well (see below).
Direct Wide Queue Connections
The ConnX Baseband Engine is truly unique in its ability to use direct connections with high-bandwidth queues between cores. This means you don't have to go through the cycle-consuming bus! This is a major revolution and provides RTL-like speed between processors and/or between processors and RTL blocks.
Tensilica's direct interfaces let you bypass the bus and go direct for maximum performance.
By using Tensilica's unique 160b input and ouput queues, you can implement hardware message passing at 8 BG/sec. Tensilica provides full hardware handshake and software support to implment data sharing and synchronixation among cores.
This enables much lower energy and much higher bandwidth than bus-based sharing.
2-8 ConnX Baseband Engines for Up to 250 GOPS
You can connect two to eight ConnX Baseband Engines for maximum performance and get up to 250 GOPS in a powerful shared-memory baseband processor platform. When eight engines are used, this high performance platform provides 64 MACs per cycle, over 100 RISC operations per cycle sustained, and 440K 2048pt complex FFTs per second.
Typical 4-engine configuration
Distributed dataRAM space is visible to all engines and accessed across 128b pipelined interconnect. Aggregate inter-engine bandwidth is 64 bytes per cycle.
The write-buffered interface creates parallelism between aggregate 50Gb/sec processor load/store data bandwidth and 25 Gb/sec inter-engine data bandwidth at 400 MHz.
Tensilica provides native SystemC modeling of multi-engine processors, including cycle-accurate and fast "turbo" mode bit-accurate simulation.
