HiFi 2 Audio DSP Product Brief
Cut DSP Development Time - Get High Performance From C, No Assembly Required
Optimizing a DSP Architecture for Wireless Baseband
A Designers Guide to HD Video Pre- and Post-Processing
Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC
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Tensilica DSP Targets LTE Advanced - Microprocessor Report review of ConnX BBE64
Tensilica Plays Baseband - New ConnX Core Aims for Low-Power Wireless Communications - Microprocessor Report review of ConnX BBE16
Tensilica Xtensa LX Processor with Vectra LX - BDTI
The ConnX Baseband Engine is very efficient because it has an application-specific instruction set optimized for DSP functions with native support for FFT, FIR filters, and complex matrix operations. By implementing many functions in hardware, the ConnX Baseband Engine gets the performance needed for 4G applications. Special features include:
The ConnX Baseband Engine is built on the baseline Xtensa RISC architecture, which implements a rich set of generic instructions optimized for efficient embedded processing. The power of the Connx Baseband Engine comes from a comprehensive DSP instruction set with approximately 285 instructions in three slots.
A wide variety of load/store operations supports six different addressing modes with support for 16b/32b scalar and vector data types. Unaligned load/stores with masking deliver full bandwidth loads and stores for unaligned data.
Multiply operations include complex and scalar 18bx18b multiply, multiply-round, multiply-add and multiply subtract functions. Complex-number functions include support for conjugate arithmetic and magnitude operation as well as full precision arithmetic and saturated/rounded outputs. The Connx Baseband Engine is capable of performing up to 16 multiplies per operation. A wide variety of rich arithmetic, logical and shift operations are supported for up to eight data words per cycle.
The Connx Baseband Engine directly supports single cycle radix-2 and radix-4 butterfly operations enabling efficient high-speed FFT implementations. Support for a single cycle 4-tap FIR filter with complex taps and single cycle 16-tap FIR filter with real taps allows efficient filtering operations. Additional specialized instructions include divide, reciprocal square root and arbitrary shuffling.