Products
ConnX Baseband Engine ConnX BBE16
Product Briefs
HiFi 2 Audio DSP Product Brief
White Papers
Cut DSP Development Time - Get High Performance From C, No Assembly Required
Optimizing a DSP Architecture for Wireless Baseband
A Designers Guide to HD Video Pre- and Post-Processing
Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC
See our complete white paper library
Analyst Reports
Tensilica DSP Targets LTE Advanced - Microprocessor Report review of ConnX BBE64
Tensilica Plays Baseband - New ConnX Core Aims for Low-Power Wireless Communications - Microprocessor Report review of ConnX BBE16
Tensilica Xtensa LX Processor with Vectra LX - BDTI
ConnX BBE16 - Leading Performance per Area and Power DSP for Wireless Baseband Communications
- Introduction - A High-Performance DSP
- Program in C, Not Assembly
- Optimizing Compiler with Support for SIMD Vectorization
- Direct Connectivity to Hardware Accelerated Blocks
- Scalable Architecture for Maximum Performance
- Toolkits Speed the Design Process
Introduction - A High-Performance DSP
The ConnX BBE16 Baseband Engine is a high performance DSP designed for use in next-generation communication baseband processors such as those found in LTE and 4G cellular radios and multi-standard broadcast receivers. The high computation requirements in such applications require new and innovative architectures with a high degree of parallelism and efficient I/O. The ConnX BBE16 meets these needs by combining an 8-way SIMD, 3-issue VLIW processing pipeline with a rich and extensible set of interfaces.
The ConnX BBE16 is built around a core vector pipeline made of 16 18bx18b MACs. These multipliers and associated adder and multiplexer trees enable operations such as FFT butterflies, parallel complex multiple operations and signal filter structures. The results of these operations can be full precision or truncated/rounded/saturated and shifted to meet the needs of different algorithms and implementations.
ConnX BBE16 in an LTE System
The instruction set has been optimized for performance of DSP kernel operations such as FFT and FIR as well as matrix multiplies. Acceleration has been added for a wide range of key wireless functions giving very high performance in wireless applications.
The ConnX BBE16 supports programming in C supported by a vectorizing compiler. Automatic vectorization of scalar C and full support for vector datatypes allows the development of algorithms without the need to program at the assembly level. Native C operator overloading is supported for natural programming with standard C operators on real and complex vector data types.
A Simplified Block Structure of the ConnX BBE16
(click on picture for larger version)
Program In C, Not Assembly
Because of the ConnX Baseband Engine's Optimizing Compiler, designers can use standard C code - not assembly - to speed the design effort. The compiler automatically vectorizes ANSI C code:
Optimizing Compiler with Support for SIMD Vectorization
For the ConnX Baseband Engine DSP, Tensilica offers efficient compiler support including automatic code scheduling, software pipelining, and SIMD vectorization of ANSI C code. In addition, the ConnX Baseband Engine compilers include direct access to all of the advanced architecture features via embedded functions. Together, these compiler features enable assembly code performance and code density without the time and risk of assembly code programming.
Direct Connectivity to Hardware Accelerated Blocks
The ConnX BBE16 DSP has the same configuration features as all Xtensa LX DPU cores. These include user defined dedicated interfaces with single cycle access to/from the ConnX BBE16 ALU to external hardware blocks. There can be up to 1024 interfaces, which can be either GPIO interfaces (ports) or FIFO interfaces (queues), each of which can be upto 1024-bits in width.
ConnX BBE16 Features Flexible I/Os - Bypassing the System Bus for Maximum Performance
Couple these interfaces with the VLIW architecture and it is possible to communicate directly from the ConnX BBE16's dedicated ALUs to the external hardware blocks.
These interfaces offer fully deterministic cycle timing, which is under software control. They offer very high performance, low power connectivity. All of this is fully integrated into ConnX BBE16 and development tools.
Scalable Architecture for Maximum Performance
While many designs will only require one ConnX Baseband Engine, this architecture can be scaled easily with up to eight instances, providing over 250 GOPS (Giga Operations Per Second) performance. See this section for more information on how one to eight ConnX Baseband Processors can be designed into a system.
Toolkits Speed the Design Process
In addition to the optimizing compiler, Tensilica offers two Eclipse-based toolkits to speed the design process. The Xtensa Processor Developers Toolkit is a set of powerful yet easy-to-use tools for processor customization. Designers can pick from several processor options (memories, interfaces, etc.), run the pipeline-modeled, cycle-accurate instruction set simulator or the high-speed instruction-accurate simulator, and perform system modeling with these proven tools.
The Xtensa Software Developers Toolkit provides a comprehensive collection of code generation and analysis tools that speeds the development process. The Xtensa software development environment is generated - automatically - from the same database as the processor hardware description so designers are guaranteed a perfect match. All configuration options are supported, so there is no need to manually edit or extend the tools. This approach ensures correctness and consistency by construction. Designers get a compiler, linker, assembler, and debugger tuned exactly - and matched exactly - to their tailored processor hardware. The software development environment includes powerful source-level multi-core debugging with flexible data-type display and profiling of both performance and energy to support rapid development of optimal system solutions.
