ConnX Turbo16MS Multistandard Turbo Decoder

Products » Comms DSP » ConnX DPUs » ConnX Turbo16MS

ConnX Turbo16MS Multi-standard Turbo Decoder

Hardware Performance, Software Flexibility

Features

  • 3GPP and HSPA+ turbo decoding
    • Supports all block sizes from 40 to 5114 bits
    • Supports 85 Mbps decoding with full 8 iterations
    • Extrinsic log-likelihood ratio (LLR) based early termination for reduced power operation
  • 3GPP LTE specification turbo decoding
    • Supports all block sizes from 40 to 6144 bits
    • Supports 150 Mbps with 8 full iterations (operating frequency of 385 MHz)
    • Code block CRC-based early termination for reduced power operation
  • Block-by-block change of physical layer mode (HSPA+/LTE), block length, and number of iterations
  • 8-window parallel decoding, with option of 4/2/1-window parallel decoding for smaller block length codes
  • One cycle per 16 bits for each ALPHA / BETA update
  • 6-bit precision for input LLR
  • Confidence accumulation functionality supports early termination

Benefits

  • LTE turbo decoding of up to 150 Mbps data streams with eight full iterations
  • HSPA+ turbo decoding of up to 85 Mbps data streams with eight full iterations
  • Small size and low power
    • Single processor with software programability allows multi-standard turbo decoder implementation
  • Support for cycle and power reduction by early termination
  • Software programmability to support multiple I/O formats
  • Road map to encompass future evolutions of the LTE/HSPA+ standards

Enormous Computation Performance for Multi-Standard (LTE and HSPA+) Turbo Decoding

The ConnX Turbo16MS is a high-performance dataplane processor unit (DPU) specifically designed for decoding of LTE Turbo codes on data streams of up to 150 Mbps and HSPA+ data streams of up to 85 Mbps. This performance is required for 3.9G and 4G cellular radios and multi-standard broadcast receivers.

ConnX Turbo16MS is based on Tensilica's Xtensa processor and has been optimized in two areas. First, a customized instruction set has been developed for LTE and HSPA+ turbo decoding. Second, it uses parallel execution for very high data bandwidth computation. This includes the 5-issue VLIW capability and the two load/store units that allow loading of dual memories in a single cycle. There are also 23 very tightly coupled scratch pad memories for storing a priori and state values that are accessed by instructions in parallel. This results in up to five memory accesses per cycle. Only this level of parallelism can give ConnX Turbo16MS the performance needed for multi-standard turbo decoding.

Some of the key architectural features include:

  • 5-issue VLIW for efficient parallel operations
  • Dual 128-bit load/store units
  • Optimized register files for turbo decoding
  • Dedicated TIE Lookup memory for a priori and state values

The ConnX Turbo16 uses two MAP decoders. Each decoder performs two passes on the data. This is done with an 8-window scheme operated in parallel, with two bits per cycle. The operation of the MAP decoders is controlled by instructions, with data being loaded in parallel to execution of the 16-way SIMD engine. Interleaving and de-interleaving is performed at the same time as memory reads or writes.

Because ConnX Turbo16MS is a processor, software algorithms can be altered to suit specific customizations in performance and input-output format as needed. Optimized software for HSPA+ and LTE is provided and is free for customer modification and use.

Programming Model

ConnX Turbo16MS is a highly optimized dataplane processor for turbo decoding. To enable a customer to quickly use this processor, a library is provided. The library contains API functions for LTE and HSPA+, which performs the fundamental Turbo block decode operation. This function can be called by the customer's higher level algorithm, implementing the turbo decoding system block.

Toolchain

The ConnX Turbo16 comes with a complete set of tools.  A comprehensive instruction set simulator (ISS) allows developers to quickly simulate and evaluate performancis integrated into a System C (XTSC) at transaction-level and pin-level system modeling to enable simulation of the ConnX Turbo16MS core and memories.

The toolset includes a high-performance C/C++ compiler with support for automatic issue of pipelined VLIW instructions. This comprehensive tool set also includes the linker, assembler, debugger, profiler, an energy estimation tool and graphical visualization tools. All major back-end EDA flows are supported for different geometries and process technologies.

Native simulation using C-Stub can enable easy integration of the software model of Turbo16MS into a larger overall C/C++ system model.

 

 

Marketing Agency