ConnX Atlas LTE Reference Architecture

Product Briefs

ConnX D2 Product Brief

ConnX Baseband Engine Product Brief

ConnX Atlas LTE Reference Architecture Product Brief

545CK Product Brief

Xtensa LX2 with Vectra Product Brief

HiFi 2 Audio DSP Product Brief

388VDO Video DSP Product Brief

White Papers

Cut DSP Development Time - Get High Performance From C, No Assembly Required

Optimizing a DSP Architecture for Wireless Baseband

A Designers Guide to HD Video Pre- and Post-Processing

Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC

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Presentations

The Five Pitfalls of 4G Baseband SOC Design

Everything You Wanted to Know About Video Processing - but Were Afraid to See

Everything You Wanted to Know About Blu-ray Audio - but were Afraid to Hear

Application Notes

Turbo Coding on Xtensa Processors

Implementing the Fast Fourier Transform (FFT)

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Analyst Reports

Tensilica Plays Baseband - New ConnX Core Aims for Low-Power Wireless Communications - Microprocessor Report

Tensilica Xtensa LX Processor with Vectra LX - BDTI

Kick Start Your LTE PHY Development

The ConnX Atlas LTE reference architecture implements the complete 3GPP Long Term Evolution (LTE) layer 1 PHY - including the computationally demanding Turbo decoder - in a completely processor based, fully programmable DSP core reference architecture.  The Atlas reference architecture consists of seven highly optimized application-specific DSPs and DPUs (dataplane processing units).  Each of the seven IP cores is uniquely optimized for different components of the full Layer 1 LTE PHY and tailored to meet the low-power requirements of user equipment (handset) devices.

The ConnX Atlas reference architecture is intended as a starting point for design teams implementing LTE baseband systems.  A design team will integrate the Atlas components together with the Layer 2 design elements and system interconnect elements of the design team's choosing.  The components of the Atlas architecture are modular. A designer may opt to deploy all seven modules and thus not require any dedicated hardware accelerators.  Or a design team may opt to re-use pre-existing RTL blocks in lieu of one or more of the Atlas components.

Tensilica's class-leading simulation technology delivers both a cycle-accurate, pipeline-modeled System C model of the entire seven-core Atlas system and a high-performance, cycle-count accurate, fast functional model of the Atlas architecture.

Atlas is fully software programmable, hence system operation can be modified post-silicon to adapt to changes and evolutions in the LTE standard, or to support related standards.  Size and power consumption of the ATLAS reference architecture is similar to those achieved with hardwired logic. In some cases the intelligence of a processor to monitor activity and reduce computation when not needed reduces power consumption below that of a hardwired system.

A Simplified Block Structure of the ATLAS LTE Reference Architecture

Block Functions

The following table explains the composition of each of the seven modules in the Atlas LTE Reference Architecture.