ConnX Atlas LTE Reference Architecture

Product Briefs

ConnX D2 Product Brief

545CK Product Brief

ConnX BBE16  Product Brief

ConnX SSP16 Product Brief

ConnX BSP3 Product Brief

ConnX Turbo16 Product Brief

ConnX BBE64 Product Brief

HiFi 2 Audio DSP Product Brief

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Cut DSP Development Time - Get High Performance From C, No Assembly Required

Optimizing a DSP Architecture for Wireless Baseband

A Designers Guide to HD Video Pre- and Post-Processing

Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC

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Analyst Reports

Tensilica DSP Targets LTE Advanced - Microprocessor Report review of ConnX BBE64

Tensilica Plays Baseband - New ConnX Core Aims for Low-Power Wireless Communications - Microprocessor Report review of ConnX BBE16

Tensilica Xtensa LX Processor with Vectra LX - BDTI

Example Baseband Modem - Atlas Reference Architecture

The ConnX Atlas LTE reference architecture implements the complete 3GPP Long Term Evolution (LTE) layer 1 PHY - including the computationally demanding Turbo decoder - in a completely processor based, fully programmable DSP core reference architecture.  The Atlas reference architecture implements a fully programmable SDR, all controlled by software. All of the processors involved use the same easy software development, debug and simulation environment. You can easily partition your algorithm into these cores with simple synchronization.

Tensilica's UE CAT4 PHY Implementation is 20% Smaller and 30% Lower Power

The ConnX Atlas reference architecture is intended as a starting point for design teams implementing LTE baseband systems.  A design team will integrate the Atlas components together with the Layer 2 design elements and system interconnect elements of the design team's choosing.  The components of the Atlas architecture are modular. A designer may opt to deploy all or just some of these processors.  Or a design team may opt to re-use pre-existing RTL blocks in lieu of one or more of the Atlas components.

Tensilica's class-leading simulation technology delivers both a cycle-accurate, pipeline-modeled System C model of the entire Atlas system and a high-performance, cycle-count accurate, fast functional model of the Atlas architecture.

Atlas is fully software programmable, hence system operation can be modified post-silicon to adapt to changes and evolutions in the LTE standard, or to support related standards.  Size and power consumption of the ATLAS reference architecture is similar to those achieved with hardwired logic. In some cases the intelligence of a processor to monitor activity and reduce computation when not needed reduces power consumption below that of a hardwired system.

Block Functions

You can find out more about the major blocks in the architecture by going to the following pages:

• ConnX BBE16 Baseband Processor
• ConnX SSP16 Soft Stream Processor
• ConnX BSP3 Bit Stream Processor
• ConnX Turbo16MS Multistandard Turbo

All of these dataplane processing units (DPUs) are developed from the same Xtensa processor technology so they have the same base ISA and are supported by the same unified single development environment and tool chain.

You can mix and match this with your existing hardware blocks, and you can use multiple instances of these DSPs and DPUs depending on your requirements. See some examples, below.

Why is Tensilica's Solution So Efficient?

Tensilica offers developers of wireless communication modem systems a range of DSPs and DPUs so they can develop modems optimized for their specific requirements. No one DPU is perfect for every single task. Therefore we've created specally optimized DPUs for the most popular tasks. With these optimizations, Tensilica is able to save more in area and power than competing solutions.

We start with an efficient DSP - either the ConnX BBE16 for LTE or the ConnX BBE64 for LTE Advanced. These DSPs are optimized for OFDM specification DSP filter computeration. They handle the main "heavy lifting" of the baseband front-end, and have been developed to give very high performance at a small size and low power.

Other non-OFDM DSP-specific tasks are off-loaded from the main DSP, allowing the main DSP to be run at a lower clock frequency for lower power. The ConnX SSP16 does the HARQ processing, soft bit descrambling, soft deinterleaving, and soft rate de-matching required for soft bit processing. The ConnX BSP3 does the FEC encoding, CRC, bit scrambling, and bit interleaving for the bit processing requirements. And the higly efficient ConnX Turbo16MP performs the turbo functions for 3GPP and HSPA+.

Sharing the computational load across multiple optimized cores lets you greatly reduce the MHz or each core. Reducing the MHz target by 30% can reduce core size by 40% and core power consumption by 60%.

Implementing a LTE Modem

The table below shows the number of Tensilica DPUs required to implement a baseband modem that meets the peak MHz requirements.

Note: To offload the soft stream and bit processing computations, you only need a single ConnX SSP16 and ConnX BSP3. The main computation is performed by the ConnX BBE16 DSP, which is optimized for OFDM DSP filter computations. If you need extra performance for higher level infrastructure applications, more than one ConnX BBE16 can be used. This helps keep the overall size to a minimum and lowers power significantly.

Here's a simple diagram that shows a comparison of Tensilica's single ConnX BBE16 DSP core and two offload engines (ConnX SSP16 and ConnX BSP3) with a conventional single large DSP implementation.

Tensilica's approach is much more efficient in area and power