ConnX 545CK DSP

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ConnX 545CK - The Fastest DSP Core

Contents

Features

  • Highest performance and efficiency of any licensable DSP core
  • 3-issue VLIW DSP with 8-way SIMD units
  • Compiler automatically vectorizes code
  • DSP instructions native to single core, modeless switching between 16-, 24- and 64-bit instructions
  • Dual 128-bit load/stores
  • Eight 16-bit multipliers that operate in SIMD mode
  • 16-entry, 160-bit-wide vector register file
  • Two 128-bit load/store units
  • 32-bit input/output FIFO interfaces
  • Viterbi convolutional coder accelerator
  • AHB-lite and AXI bridges

Benefits

  • Very high and flexible computational performance
  • Performance headroom allows operation at lower frequency to reduce power consumption
  • Single core, single development environment due to native DSP instructions
  • Ideal for communication baseband applications
  • Very high I/O throughput; higher than XY DSPs
  • Bypass system bus and communicate directly via FIFO interfaces
  • Drop into existing AMBA™-based systems

Highest Performance DSP Core

The ConnX 545CK is the highest performance licensable DSP IP core. The ConnX 545CK, which combines a base CPU controllers and a DSP containing eight parallel 16-bit single-cycle MAC units, allows system control and industry leading data processing throughput in a single core with a single compiler and single instruction stream. The ConnX 545CK can sustain eight simultaneous MAC operations on independent data pairs per cycle, utilizing the 160-bit vector registers.

As in all Xtensa ISA-based architectures, 16-, 24- and 64-bit VLIW instruction bundles can be freely intermixed in the instruction stream with no processor mode switching to decrease performance. All software development tools (compiler, linker, debugger, instruction set simulator) have been enhanced to enable access to DSP-related and control hardware through standard C/C++ source code.

In addition to the data processing gains realized through parallel multiplier hardware, the ConnX 545CK includes support for other DSP-related operations, such as zero-overhead looping, clamps (saturating arithmetic), max/min value, normalize, and sign extend.

The ConnX 545CK is an industry leading combination of an efficient 32-bit RISC controller and an extremely high-performance DSP in a single licensable IP core. It eliminates the need to develop SOCs with separate control and DSPs.

Frequency, Area and Power Specs


130G
90G
65GP
Speed Optimized Area
Optim		 Speed Optim Area
Optim		 Speed Optim Area Optim
Area (mm2) post-synthesis
 2.48 2.22 1.29 1.09 0.805 0.66
Cell a rea (mm2) post-layout
 3.58 2.88 1.76 1.34 1.115 0.735
Freq (MHz) post-layout
 220 N/A 350 N/A 520 N/A
Power (mW/MHz) post-layout
 0.35 0.29 0.15 0.124 0.14 0.08

All EDA numbers are for Sage-X libraries.
Area and frequency at worst operating condition (0.9 * Vdd, 132 C)
Power at typical operating condition (1.0 * Vdd, 25 C)
All area, power, and frequency numbers are representative only, and subject to variation based on each user's chosen process technology, cell library, and design tools.
*Area is post synthesis, post layout, assuming 50% utilization.

Performance Comparison

BDTI benchmarks

ConnX 545CK is faster than every other licensable DSP core or CPU core tested by BDTI (higher is better)

All scores use worst-case clock speeds for the TSMC CL013G process and ARM Artisan SAGE-X library.
The BDTIsimMark2000™ is a summary measure of DSP speed. See www.BDTI.com for info. Scores © 2007 BDTI.

Low Power

In addition, the ConnX 545CK achieves a BDTIsimMark2000TM per-mW score of 80. This is over 2x more energy efficient than any other core benchmarked by BDTI to date (as of July 2009).

Block Diagram of the ConnX 545CK Core

545CK block diagram

 

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