Create Your Own Proprietary Value-Added Processor or DSP Core
Do you want to make products that can't be copied so they can be truly your own? If you use industry standard processor cores, your products might come out looking like everyone else's products. But you can use Tensilica's patented, automated software tools to create your own version of an Xtensa processor with a proprietary instruction set that's virtually impossible to copy. It's not only unique, optimized for your application, but it's very likely that it will be faster and use less power than a standard processor core. And, you can improve your return on investment (ROI) using Tensilica's processors as well.
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Improving Your ROI Using Tensilica's Xtensa Processors
In a decision to design a chip, the relevant ROI is about the volume of chips, margin per chip, and cost of design. Using Xtensa configurable processors affects each factor in that equation:
- A more programmable chip means more volume, because more related systems can share one common design.
- Programmability means higher margin, because new capabilities can be quickly added in software, which adds little to chip area or cost.
- Automatic design of the individual configurable processor blocks and easier integration of all of the subsystems into a complete SOC translates into less design time, smaller design teams, and lower risk of redesign, since more of the system functionality is implemented in software and can be changed to adapt to changing standards or market requirements.
Together, these drive the ROI for chip design in the right direction.
Tensilica's Guaranteed, Correct-by-Construction Design Process
Tensilica's design methodology was made for designers with little or no experience with processor design to optimize an Xtensa processor. And your designers cannot create a "broken" processor - we make sure of that using our correct-by-construction modification process. Your designers use Tensilica's patented, automated tools to easily add instructions to make your Xtensa processor unique. You'll get an automatically produced matching software tool chain to take advantage of the accelerations you've built into your customized processor, so other companies can't get the performance and power savings you've built into your design.
To find out more about the design process, follow these links:
Tensilica's Modern Processor Architecture
Unlike most popular 32-bit RISC standard processors that were designed for workstation applications in the 1980s, Tensilica's Xtensa architecture was designed in the late 1990s for embedded, low-power tasks. The Xtensa architecture starts with base ISA features common to all Xtensa cores. SOC developers can configure Xtensa processors from menus of predefined options and add functional units of their own design to optimize algorithm performance. Find out more about this outstanding architecture. See how this architecture results in top benchmark scores.
Using Xtensa Processors for Digital Signal Processing
Many designs use a standard 32-bit processor coupled with a DSP core to accelerate the digital signal processing performance. However, with Xtensa processors, there's no need for a separate DSP - the DSP functions can be built right into the processor itself, eliminating the need to transfer data on a slow processor bus back and forth between the two. Using our easy-to-use methodology, Tensilica was able to build the Diamond Standard 545CK, the fastest processor core ever benchmarked by BDTI. Here's more information on how you can build a high-performance DSP right into your Xtensa processor.
Getting Better Performance and Using Lower Power than Standard RISC Cores
Because Xtensa processors are based on a newer, post-RISC architecture, they get better performance than standard RISC processors. Xtensa processors were used as the base for Tensilica's Diamond Standard family of processor cores. See how they stack up against popular ARM processors. Xtensa processors also topped all of the EEMBC processor core benchmarks for networking, office automation, and consumer products.
Xtensa processors use less power because the architecture integrates fine-grained and course-grained clock gating. Also, Tensilica has made many enhancements to the processors' memory architecture to make memory accesses, often the cause of power problems, much more efficient and lowering overall power.
And don't worry about increasing power as you customize your own Xtensa processor. Our Xenergy tool will help keep your designers on track, providing valuable feedback on the power impact of every single change. Find out about all of the things Tensilica built into the Xtensa processors to keep power usage to a minimum.
Eliminate the Need for Extra Hardware Blocks
The problem with standard RISC processors is that there's always something (or a lot of things) that just won't run fast enough on that processor, so extra logic (RTL or hardware) blocks need to be designed. And that's where the whole SOC project slows down. Hardware blocks are hard to design and even harder to verify. And since they're fixed function blocks, they can't be changed in software once committed to silicon.
By accelerating functions right inside the Xtensa processors, you can eliminate the need for extra hardware blocks and their time consuming design and verification process. Find out how Xtensa processors can lower verification effort and time, lower power, allow for the reuse of the same block for different functions, and give you the flexibility to upgrade algorithms post silicon.
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