Emulating Diamond Standard Processors

Product Briefs

Diamond 106Micro Product Brief

Diamond 108Mini Product Brief

Diamond 212GP Product Brief

Diamond 233L Product Brief

Diamond 570T Product Brief

White Papers

10 Tips for Successful SOC Design

Diamond Standard Core Family

Xtensa Architecture White Paper

Evaluation Software

Free 15-day Software Eval

Emulation Strategies

Tensilica's customers can deploy a variety of strategies for emulation of SOC designs employing Diamond Standard processors.

Some Diamond Standard designers use the RTL source code provided to support FPGA-based boards of their own design as part of a comprehensive SOC methodology.

Other Tensilica customers use commercial emulation systems in their SOC design process. EVE (Emulation and Verification Engineering) is Tensilica's recommended provider of high-capacity FPGA-based system emulators for SOC designs. EVE's ZeBu products are targeted for use in the system-integration phase of the design cycle where multiple logic blocks and embedded software must be verified together. EVE and Tensilica have partnered to provide seamless integration of Tensilica debug tools into the EVE development software environment.

FPGA Board Support

Software developers can use a Virtex6 FPGA ML605 evaluation board to speed their software design, debug and program optimization processes.

Tensilica’s software developers’ toolkits (SDKs) – consisting of an IDE (the Xtensa Xplorer integrated design environment), code development toolchain and Tensilica’s instruction set simulator (ISS) – work seamlessly with either Avnet FPGA board. The software tools include libraries that enable software developers to use standard C library functions such as printf to print out to the host PC and read/write from the hard disk of the host PC.

Designers using Tensilica’s processors can take maximum advantage of to evaluation board to gather extensive hardware-based profiling information. With hardware-based profiling, developers can get s an execution profile of the program, which allows the developer to quickly pinpoint execution hotspots. This profile can be viewed graphically within Tensilica’s Xtensa Xplorer IDE.

Using feedback compilation, a developer can set a flag so the compiler instruments the compiled code to collect statistics on the number of times branches (loops, jumps, etc.) are taken or not taken during execution on the Avnet Xilinx Development Kit board. The Xtensa C/C++ compiler then uses these run-time generated statistics and recompiles the program to optimize (a) for speed by placing most frequently taken branches in straight-line code, and (b) for code size by compiling less frequently executed routines for code size rather than speed. The feedback-based compilation method speeds up applications between 5 to 15 percent and reduces code size by up to 15 percent.

Additionally, the Ethernet interface on the boards make them ideal for running an operating system such as Linux and the associated TCP/IP stack and network file systems.

Tensilica supplies users with precompiled FPGA bitstreams that support this board.