Products
Diamond Standard Processors - Beats the Competition Every Way
Product Briefs
Diamond 106Micro Product Brief
Diamond Software Tools Product Brief
White Papers
10 Tips for Successful SOC Design
Xtensa Architecture White Paper
Evaluation Software
See Microprocessor Report's Write-up on Diamond Processors
In Every Way: Smaller, Lower Power, Higher Performance
No matter how you look at it, Tensilica's Diamond Standard processor family is smaller, lower power, and higher performance than the equivalent competitive embedded processor. Check out the results for these Diamond Standard processors:
Competitive measurement conditions:
| Specification | Tensilica | ARM |
|
Power Consumption
|
Process - 0.13u G TSMC |
Process - 0.13u G TSMC
Library - Sage-X/HS VDD - typical Processor Load - Dhrystone loop Frequency - not maximum |
|
Maximum Frequency
|
Process - 0.13u G TSMC
Library - Sage-HS Wire-load model - Yes Worst case conditions - Yes |
Process - 0.13u G TSMC
Library - Sage-X/HS Wire-load model - ? Worst case conditions - Yes |
|
Core Area
|
Library - Sage X
Frequency - 50MHz Pre-layout |
Library - Sage-X/HS
Frequency - not maximum Pre-layout |
Data on ARM products taken from ARM public web site and product information flyers, Feb. 2007 for TSMC 0.13G process.
Diamond Standard core data is subject to change. All speed, power, and are metrics are subject to variation based upon user's design tools, libraries, and fab choices.
Diamond Architecture - More Modern, More Efficient
The Diamond Standard processor core family is based on the Xtensa processor architecture, proven in millions of shipping products. Because it was developed in the late 1990s, it is more efficient than many older competitive architectures. The 24/16-bit instruction set architecture gives a 30% smaller code size than ARM and 50% smaller than MIPS at the same performance level, as shown below.
Tensilica's Xtensa architecture is much more efficient and results in smaller code size than ARM and MIPS.
(click here for larger version)
For more information on the Xtensa architecture, see our Xtensa Products section.
Diamond Standard 106Micro
| ARM 7TDMI | Diamond 106Micro | Cortex M3 | ARM 968E-S | |
|
Max Frequency (0.13u G)
|
150 MHz | 250 MHz | 135 MHz | 270 MHz |
|
Dhrystone MIPS
|
142 | 305 | 169 | 289 |
|
Pipeline
|
3-stage | 5-stage | 3-stage | 5-stage |
|
Local Memories
|
Single data/ instruction interface | Separate instruction and data memories (TCMs) | No local memories (TCMs) | Separate instruction and data memories (TCMs) |
|
Power (mW/MHz) pre-layout (0.13G)
|
0.17 | 0.07 | 0.12 | 0.11 |
|
Area and power for all cores includes system bus and interrupt controller. 106Micro area includes trace port, instruction and data watch-point registers, which are not included in ARM7 and Cortex M3 area.
|
||||
The Diamond 106Micro is Smaller and Faster than Popular ARM Cores
Diamond Standard 108Micro
|
Diamond 108Mini
|
ARM 968E
|
|
|
Max Frequency (0.13u G) worst case conditions (Sage-HS library, speed optimized)
|
250 MHz | 240 MHz |
|
Dhrystone MIPS
|
335 | 260 |
|
Power (mW/MHz) (0.13u G) pre-layout (Sage-X library)
|
0.08 | 0.1 |
|
Arithmetic functions
|
32x32 Multiplier 32-bit Divider |
16x32 Multiplier No Divider |
|
Direct interfaces
|
Two 32-bit GPIO ports | No direct interfaces |
|
Interrupts and timers
|
Integrated interrupt controller (22) & timers (3) | Does not include interrupt controller & timers |
Diamond Standard 212GP
|
ARM 946E-S
|
Diamond 212GP | |
|
Max Frequency (0.13u G) worst case conditions (Sage-X library, optimized for speed)
|
210 MHz | 250 MHz |
|
Dhrystone MIPS
|
231 | 345 |
|
Power - mW per MHz (0.13u G) (Sage-X library, optimized for area)*
|
0.31 | 0.2 |
|
Area (Sage-X library, optimized for area)
|
0.97 mm2 | 0.64 mm2 |
|
Code Density
|
Mode bit to switch between 32- and 16-bit instructions | Modelessly switch between 24- and 16-bit instructions |
|
Number of Interrupts
|
3 | 22 with 6 priority levels (with integrated interrupt controller) |
|
Number of Integrated Timers
|
0 | 3 |
|
Direct Interface Ports/wires
|
No | 32-bit input port, 32-bit output port |
|
* Power depends on operating conditions, standard cell libraries, performance targets, and processor load. See white paper: Processor Core Power Specs: A Cautionary Tale
|
||
Diamond Standard 232L
|
ARM 926EJ-S
|
Diamond 232L | |
| AREA & PERFORMANCE | 50% Smaller | |
|
Max Frequency (0.13u G) worst case, Sage-X library, optimized for speed
|
250 MHz | 215 MHz |
|
Dhrystone MIPS
|
275 | 288 |
|
Area - Sage-X library, optimized for area
|
1.45 mm2 | 0.78 mm2 |
| POWER | Much Lower Power | |
|
mW per MHz (0.13u G, Sage-X library, optimized for area)*
|
0.36 | 0.21 |
|
mW at same MHz
|
77 mW @ 215 MHz | 45 mW @ 215 MHz |
| FEATURES | More Features | |
|
Code Density
|
Mode bit to switch between 32- & 16-bit instructions | Modelessly switch between 24- and 16-bit instructions |
|
Arithmetic functions
|
16x32 Multiplier No Divider |
32x32 Multiplier 32-bit Divider |
|
Zero-overhead Looping
|
No | Yes |
|
Number of Interrupts
|
3 (no integrated interrupt controller) | 22 with 6 priority levels (with integrated interrupt controller) |
| Number of Integrated Timers | 0 | 3 |
|
* Power depends on operating conditions, standard cell libraries, performance targets, and processor load.
|
||
Diamond Standard 570T
| ARM 1156T2-S | Diamond 570T | ARM 1136J-S | |
| AREA & PERFORMANCE | 1/3 the die area, much more efficient/MHz | ||
|
Max Frequency (90G) Sage-HS library, optimized for speed
|
620 MHz | 892 (EEMBC equivalent freq) (Actual=388 MHz) | 620 MHz |
|
Instruction Issue (per cycle)
|
1 | 3 | 1 |
|
Dhyrstone MIPS/MHz
|
1.20 (est.) | 1.59 | 1.20 |
|
Area (90G, pre-layout) Sage-HS library, optimized for speed
|
1.75 mm2 | 0.62 mm2 | 1.8 mm2 |
| POWER | Lower power than ARM11 | ||
|
mW per MHz (90G)*
(Sage-HS library, optimized for speed) |
0.42 | 0.13 | 0.37 |
|
mW for the Same Performance
|
250 mW @ 620 MHz | 50 mW @ 388 MHz | 229 mW @ 620 Mhz |
| FEATURES | More Features | ||
|
Instruction width
|
16/32 bit | 16/24/64 bit 3-issue | 16/32 bit |
|
High throughput Data Queues
|
No | Yes (input and output) | No |
|
Direct Ports/Wires
|
No | 32 in / 32 Out | No |
|
* Power depends on operating conditions, standard cell libraries, performance targets, and processor load. See white paper: Processor Core Power Specs: A Cautionary Tale.
**EEMBC equivalent freqency - see chart below. This equates frequency based on EEMBC performance multiplier. |
|||
| ARM 1136JF-S* | ARM 1026EJ-S (Certified as core) | Diamond 570T | |
| NetMARK | 1.0 | 1.29 | 2.55 |
| ConsumerMARK | 1.0 | 1.47 | 2.91 |
| OfficeMARK | 1.0 | 1.19 | 1.64 |
| TeleMARK | 1.0 | 1.06 | 2.28 |
| Geometric Mean | 1.0 | 1.24 | 2.30 |
| Results normalized on a per-MHz basis | |||
*Results extrapolated from Freescale IMX31 device. No certified ARM1136JF-S EEMBC results have been published as of 12-31-2005.
ARM1136JF-S performance based on Freescale i.MX31 performance. Power figure for ARM per ARM’s publicly cited specifications - running at 266 MHz in 0.13 micron. Tensilica Diamond 570T running at 115MHz in 0.13 micron.
