Products
Diamond Standard Processors - Comparison Matrixes
Product Briefs
Diamond 106Micro Product Brief
White Papers
10 Tips for Successful SOC Design
Xtensa Architecture White Paper
Evaluation Software
See Microprocessor Report's Write-up on Diamond Processors
Which Diamond Standard Controller is Right for Your Application?
Tensilica's Diamond Standard processor family covers the broadest range of performance of any embedded computing architecture. Here are several charts to help you figure out which processor core is best for your needs.
Diamond Standard Controllers - From Cache-less Controller to High-Performance VLIW CPU
Diamond Standard Controllers - CPU Selector Guide
| 106Micro | 108Mini | 212GP | 233L | 570T | |
| PERFORMANCE | Speed Optimized | ||||
| Max Frequency (45nm GS, worst case conditions) |
907 MHz | 923 MHz | 835 MHz | 769 MHz | 780 MHz |
| Dhrystone MIPS/MHz | 1.22 |
1.34
|
1.38
|
1.38
|
1.59
|
| AREA (45nm GS) |
Area Optimized | ||||
| Cell Area, Post-Route |
0.045 mm2 | 0.082 mm2 | 0.113 mm2 | 0.135 mm2 | 0.158 mm2 |
| POWER | Area Optimized | ||||
| mW per MHz (45nm GS, typical conditions) | 0.013 | 0.019 | 0.027 | 0.028 | 0.034 |
| FEATURES | All Upwards Software Compatible | ||||
| Instruction Width | 16/24 bit | 16/24 bit | 16/24 bit | 16/24 bit | 16/24/64 bit 3-issue |
| General Purpose I/O Ports | No | Yes | Yes | Yes | Yes |
| High-Throughput Data Queues (FIFOs) | No | No | No | No | Yes |
Hardware Features
| 106Micro | 108Mini | 212GP | 232L |
570T
|
|
| Pipeline stages | 5 | 5 | 5 | 5 | 5 |
| Instruction width (bits) | 16/24 | 16/24 | 16/24 | 16/24` | 16/24/64 |
| Multiple instruction issue (static superscalar) | no | no | no | no | 3 issue or 2 issue |
| Local memory data path width (bits) | 32 | 32 | 32 | 32 | 64 |
| General purpose registers | 32 | 32 | 32 | 32 | 32 |
| Instruction cache size |
N/A |
N/A | 8 Kbyte | 16 Kbyte | 16 Kbyte |
| I-Cache associativity |
N/A |
N/A | 2-way | 4-way | 2-way |
| Data cache size | N/A | N/A | 8 Kbyte | 16 Kbyte | 16 Kbyte |
| D-Cache associativity | N/A | N/A | 2-way | 4-way | 2-way |
| Local instruction RAM, user selectable size, maximum size | 128 Kbyte | 128 Kbyte | 128 Kbyte | N/A | 128 Kbyte |
| Local data RAM, user selectable size, maximum size | 128 Kbyte | 128 Kbyte (dual) | 128 Kbyte | N/A | 128 Kbyte |
| XLMI Interface | no | no | yes | no | yes |
| Input/output ports (32 bits wide) | no | yes | yes | yes | yes |
| Input/output queues (32 bits wide) | no | no | no | no | yes |
| System interface (PIF) width | 32 | 32 | 32 | 32 | 64 |
| MUL 16 | yes | yes | yes | yes | yes |
| MAC 16-bit single cycle | no | no | yes | yes | yes |
| 32x32 MUL32 | yes | yes | yes | yes | dual |
| 32-bit integer divide | no | yes | yes | yes | yes |
| Sign Extend, NSA, MIN/MAX | yes | yes | yes | yes | yes |
| Zero-overhead looping | no | no | yes | yes | yes |
| Specialized DSP instructions | no | no | no | no | no |
| External interrupts | 12 | 16 | 16 | 16 | 16 |
| Timer interrupts | 1 | 3 | 3 | 3 | 3 |
| Software interrupts | 1 | 2 | 2 | 2 | 2 |
| Non-maskable interrupt | yes | yes | yes | yes | yes |
| On-chip debug (OCD) | yes | yes | yes | yes | yes |
