Diamond Standard 570T

When You Need Performance


Features

  • Two- or three-issue, static-superscalar Very Long Instruction Word (VLIW)
  • Modeless switching between 16-, 24- and 64-bit instructionskeeps code size low
  • Compiler automatically creates VLIW instructions
  • Dhrystone 2.1: 1.59 DMIPS/MHz
  • Dual 32x32 SIMD MULs and 32-bit integer divider
  • 16-bit DSP instructions
  • 16 Kbyte, 2-way set associative insruction and data caches, programmable write-through or write-back
  • Single-cycleinstruction and data SRAM interface
  • High-speed XLMI peripheral port
  • Memory protection unit
  • 64-bit PIF interface
  • 2x32-wire GPIO ports for direct control and monitoring of peripherals
  • 2x32-bit Queue interfaces for streaming data into and out of the processor via FIFOs
  • On-chip debugging hardware
  • Embedded trace support
  • AHB-lite and AXI bridges

Benefits

  • Highest performance CPU per EEMBC benchmarks
  • Simple programming model - Compiler automaitically maps C/C++ to SIMD and VLIW to boost performance
  • High arithmetic and DSP performance, reducingneed for separate DSP
  • Fast and flexible interrupt handling
  • Bypass system bus and communicate directly via GPIO and FIFO interfaces
  • Drop into existing AMBA-based SOCs

A Static-Superscalar Controller Core

The Diamond Standard 570T is among the highest performance, highest throughput licensable CPUs available today. It combines an efficient 5-stage pipeline with a 3-issue VLIW architecture, enabling it to obtain leading performance levels on both control and DSP code.

Due to the Diamond 570T's flexible base architecture, 16-, 24-, and compound 64-bit VLIW instruction bundles can be freely intermixed in the instruction stream with no processor mode switching, thus maintaining performance while optimizing code size. The compiler automatically creates 64-bit VLIW instruction bundles if instructions can be issued simultaneously; otherwise, a single 16/24-bit instruction is issued. This capability increases code density to industry leading levels, reducing the amount of on-chip cache or memory required for storage of instructions.

The Diamond 570T includes  many standard DSP instructions that increase the performance of numerically intensive applications, plus a 32x32 multiplier and 32-bit integer divider. Example DSP instructions include: zero overhead looping, clamps (saturating arithmetic), max/min value, normalize, and sign extend. Additionally, a MAC unit enables high performance on inner loops requiring fast multiply accumulate operations.

The Diamond 570T features innovative I/O that allows data to be streamed in and out of the processor without going over the main data bus. The two 32-wire GPIO (general-purpose I/O) ports allow direct control and monitoring of peripherals. Two 32-bit FIFO port interfaces can connect to standard FIFOs for direct, predictable communication with other RTL blocks, devices and processors.

Get the 2-page Diamond Standard 570T product brief.

Frequency, Area and Power Specs

Process Flow Post-Route Cell Area (mm2) Speed (MHz) Post Prime Time Post-Route Power (mW/MHz)
65GP High-Speed 0.440 635 0.110
Low-Power 0.257 58 0.058
65LP High-speed 0.463 399 0.142
Low-Power 0.249 57 0.080
45GS High-Speed 0.283 780 0.066
Low-Power 0.158 58 0.034
40LP High-Speed 0.295 493 0.093
Low-Power 0.163 57 0.046

Block Diagram

Diamond 570T

Diamond Standard 570T Controller

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