Diamond Standard 570T

Products » Diamond Controllers » 570T High Perf

Ultra High Performance - Beats the Benchmarks

Contents:

Features

  • Ultra-high-performance RISC CPU core
  • Two- or three-issue, static-superscalar Very Long Instruction Word (VLIW)
  • Modeless switching between 16-, 24- and 64-bit instructions
  • Compiler automatically creates VLIW instructions
  • Dhrystone 2.1: 1.59 DMIPS/MHz
  • Dual 32x32 SIMD MULs and 32-bit integer divider
  • 16-bit DSP instructions
  • 16 Kbyte, 2-way set associative I & D caches, programmable write-through or write-back
  • Single-cycle I & D SRAM interface
  • High-speed peripheral port (XLMI)
  • Memory protection unit
  • 64-bit PIF interface
  • On-chip debugging hardware
  • Embedded trace support
  • 32-bit GPIO and FIFO interfaces
  • AHB-lite and AXI bridges

Benefits

  • Highest performance CPU per EEMBC benchmarks
  • Compiler maps C/C++ automatically to boost performance; simple programming model
  • High arithmetic and DSP performance, eliminating need for separate DSP
  • Fast and flexible interrupt handling
  • Bypass system bus and communicate directly via GPIO and FIFO interfaces
  • Drop into existing AMBA-based SOCs

Static-Superscalar Controller Core

The Diamond Standard 570T is among the highest performance, highest throughput licensable CPUs available today. It combines an efficient 5-stage pipeline with a 3-issue VLIW architecture, which enables it to obtain leading performance levels on both control code and DSP code, when benchmarked using EEMBC benchmarks.

Due to the Diamond 570T’s flexible base architecture, 16-, 24-, and compound 64-bit VLIW instruction bundles can be freely intermixed in the instruction stream with no processor mode switching, thus maintaining performance while optimizing code size. The compiler automatically creates 64-bit VLIW instruction bundles if instructions can be issued simultaneously; otherwise, a single 16/24-bit instruction is issued. This capability increases code density to industry leading levels, reducing the amount of on-chip cache or memory required for storage of instructions.

The Diamond 570T includes many standard DSP instructions to increase performance of numerically intensive applications, plus a 32x32 multiplier and 32-bit integer divider. Example DSP instructions include: zero-overhead looping, clamps (saturating arithmetic), max/min value, normalize, and sign extend. Additionally, a MAC unit enables high performance on inner loops requiring fast multiplication.

The Diamond 570T also includes 32-bit input/output GPIO ports and 32-bit input/output FIFO interfaces, which can be used to connect to standard FIFOs for fast communication with other RTL blocks, devices, and processors without ever using the system bus for maximum throughput.

Get the 2-page Diamond Standard 570T product brief.

Frequency, Area and Power Specs


90G
65GP
65LP
Speed Optimized Area
Optimized		 Speed Optimized Area
Optimized		 Speed Optimized Area Optimized
Area (mm2) post-synthesis
 0.55 0.46 0.35 0.26 0.3 0.244
Area (mm2) post-layout
 0.7 0.52 0.48 0.28 0.415 0.276
Freq (MHz) post-layout
 380 N/A 560 N/A 330 N/A
Power (mW/MHz) post-layout
 0.15 0.124 0.14 0.08 0.164 0.127
Simulated Leakage (mW)
 1.417 0.766 2.703 0.851 0.0288 0.0118

90G is with TSMC Sage-X libraries.
65GP is with TSMC Advantage library, Regular Vt.
65LP is with TSMC library (Synopsys), Regular Vt.
Area and frequency at worst operating condition (0.9 * Vdd, 125 C)
Power at typical operating condition (1.0 * Vdd, 25 C)
All area and speed calculations are made assuming 8KB local SRAM size
All area, power, and frequency numbers are representative only, and subject to variation based on each user's chosen process technology, cell library, and design tools.

Block Diagram of the Diamond Standard Series 570T

570T block diagram

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Diamond 570T Instruction Formats

The Diamond 570T uses 16-, 24- and 64-bit instructions. By wisely only using large instructions when needed, the Diamond 570T provides code-efficient VLIW-like performance. Four instruction formats are supported, as shown below.

570T instruction formats

The compiler automatically modelessly intermixes these different instruction formats for maximum efficiency.

 

Diamond 570T Uses Smaller Die Area and 1/3 the Power of ARM 1136/1156

ARM 1156T2-S Diamond 570T ARM 1136J-S
AREA & PERFORMANCE 1/3 the die area, much more efficient/MHz
Max Frequency (90G) Sage-HS library, optimized for speed
 620 MHz 892 (EEMBC equivalent freq) (Actual=388 MHz) 620 MHz
Instruction Issue (per cycle)
 1 3 1
Dhyrstone MIPS/MHz
 1.20 (est.) 1.59 1.20
Area (90G, pre-layout) Sage-HS library, optimized for speed
 1.75 mm2 0.62 mm2 1.8 mm2
POWER Lower power than ARM11
mW per MHz (90G)*
(Sage-HS library, optimized for speed)
0.42 0.13 0.37
mW for the Same Performance
 250 mW @ 620 MHz 50 mW @ 388 MHz 229 mW @ 620 Mhz
FEATURES More Features
Instruction width
 16/32 bit 16/24/64 bit 3-issue 16/32 bit
High throughput Data Queues
 No Yes (input and output) No
Direct Ports/Wires
 No 32 in / 32 Out No
* Power depends on operating conditions, standard cell libraries, performance targets, and processor load.