Diamond Standard 212GP - Rev B

Products » Diamond Controllers » 212GP General Purpose

A High-PerformanceGeneral-Purpose RISC CPU with Basic DSP Instructions

Contents:

Features

  • High performance with minimal die area, minimal power
  • 5-stage pipeline
  • Dhrystone 2.1: 1.38 DMIPS/MHz
  • 32x32 multiplier and 32-bit integer divider
  • 16-bit DSP instructions
  • 8Kbyte, 2-way instruction and data caches
  • 32-bit input/output GPIO ports for direct communication
  • Integrated interrupt controller with 22 interrupts at 6 priority levels
  • Three integrated timers
  • Single-cycle XLMI interface
  • On-chip debugging hardware
  • Embedded trace support
  • Comprehensive software design environment
  • AHB-lite and AXI bridges

Benefits

  • Flexible memory architecture adaptable to an extremely wide range of applications
  • On-chip debug decreases time to market
  • High arithmetic and DSP performance, eliminating need for separate DSP
  • Fast and flexible interrupt handling
  • XLMI high-speed interface for co-processors and devices
  • High performance on general purpose code
  • No memory contention between instructions and data
  • Drop into existing AMBA-based SOCs

Flexible Mid-Range RISC Controller

The Diamond Standard 212GP CPU is a high-performance, versatile, fully synthesizable 32-bit RISC CPU controller core. It is area and power efficient with a local memory architecture that provides outstanding flexibility and performance. Users can take advantage of Tensilica’s lockable cache and attach any size single-cycle instruction or data SRAM up to 128Kbytes.

Since Diamond 212GP target applications are controller related, interrupt options are extremely important. The Diamond 212GP includes a non-maskable interrupt for critical system events and six levels of interrupts consisting of a combination of external, software, and timing interrupts. This eases the development of software interrupt handlers and external interrupt priority hardware design.

Arithmetic and DSP hardware support on chip reduces the need to include a separate DSP in the system design. DSP support in the Diamond 212GP consists of a single-cycle 16x16-bit MAC unit adding four dedicated 32-bit registers and a 40-bit accumulator. Additionally, there is support for zero overhead looping, clamps (saturating arithmetic), max/min value, normalize, and sign extend.

The performance of the Diamond 212GP is extremely high: 400 MHz in a 90nm G-type process. It is capable of handling any control plane and many DSP applications because of the built-in 32x32 multiplier and 32-bit integer divider.

Get the 2-page Diamond Standard 212GP product brief.

Frequency, Area and Power Specs

90G
65GP
65LP
Speed Optimized Area
Optimized		 Speed Optimized Area Optimized Speed Optimized Area
Optimized
Area (mm2) post-synthesis
 0.4 0.32 0.248 0.183 0.223 0.17
Area (mm2) post-layout
 0.5 0.36 0.335 0.197 0.3 0.188
Freq (MHz) post-layout
 400 N/A 600 N/A 350 N/A
Power (mW/MHz) post-layout
 0.108 0.089 0.103 0.062 0.13 0.09
Simulated Leakage (mW)
 0.999 0.518 1.850 0.577 0.021 0.0076

90G is with TSMC Sage-X libraries.
65GP is with TSMC Advantage library, Regular Vt.
65LP is with TSMC library (Synopsys), Regular Vt.
Area and frequency at worst operating condition (0.9 * Vdd, 125 C)
Power at typical operating condition (1.0 * Vdd, 25 C)
All area and speed calculations are made assuming 8KB local SRAM size
All area, power, and frequency numbers are representative only, and subject to variation based on each user's chosen process technology, cell library, and design tools.

Block Diagram of the Diamond Standard Series 212GP

212GP block diagram

Check out our Diamond FREE software evaluation.

Diamond 212GP Provides Better Performance than ARM9
with Lower Power and Smaller Area
ARM 946E-S
Diamond 212GP
Max Frequency (0.13u G) worst case conditions (Sage-X library, optimized for speed)
 210 MHz 250 MHz
Dhrystone MIPS
 231 345
Power - mW per MHz (0.13u G) (Sage-X library, optimized for area)*
 0.31 0.2
Area (Sage-X library, optimized for area)
 0.97 mm2 0.64 mm2
Code Density
 Mode bit to switch between 32- and 16-bit instructions Modelessly switch between 24- and 16-bit instructions
Number of Interrupts
 3 22 with 6 priority levels (with integrated interrupt controller)
Number of Integrated Timers
 0 3
Direct Interface Ports/wires
 No 32-bit input port, 32-bit output port
* Power depends on operating conditions, standard cell libraries, performance targets, and processor load.

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