Diamond Standard 212GP - Rev B

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A High-PerformanceGeneral-Purpose RISC CPU with Basic DSP Instructions

Features

• High performance with minimal die area, minimal power
• 5-stage pipeline
• Dhrystone 2.1: 1.38 DMIPS/MHz
• 32x32 multiplier and 32-bit integer divider
• 16-bit DSP instructions
• 8Kbyte, 2-way instruction and data caches
• 32-bit input/output GPIO ports for direct communication
• Integrated interrupt controller with 22 interrupts at 6 priority levels
• Three integrated timers
• Single-cycle XLMI interface
• On-chip debugging hardware
• Embedded trace support
• Comprehensive software design environment
• AHB-lite and AXI bridges

Benefits

• Flexible memory architecture adaptable to an extremely wide range of applications
• On-chip debug decreases time to market
• High arithmetic and DSP performance, eliminating need for separate DSP
• Fast and flexible interrupt handling
• XLMI high-speed interface for co-processors and devices
• High performance on general purpose code
• No memory contention between instructions and data
• Drop into existing AMBA-based SOCs

A Flexible Mid-Range RISC Controller

The Diamond Standard 212GP CPU is a high-performance, fully synthesizable 32-bit RISC core. It is area and power efficient with a local memory architecture that provides outstanding flexibility and performance. Designers can take advantage of Tensilica's lockable cache and attach any size single-cycle instruction or data SRAM up to 128Kbytes.

Since the Diamond 212GP's target applications are controller related, interrupt options are extremely important. The Diamond 212GP includes a non-maskable interrupt for critical system events and six levels of interrupt priorities from a combination of external, software and timing interrupts. This eases the development of software interrupt handlers and external interrupt priority hardware design.

Arithmetic and DSP hardware support reduces the need to include a separate DSP in the system design. DSP support consists of a single-cycle 16x16 MAC unit adding four dedicated 32-bit registers and a 40-bit accumulator. Additionally, there is support for zero overhead looping, clamps (saturating arithmetic), max/min value, normalize, and sign extend. Arithmetic support is provided by a built-in 32x32 multiplier and 32-bit integer divider.

The Diamond 212GP features innovative I/O that allows data to be streamed in and out of the processor without going over the main data bus. The two 32-wire GPIO (general-purpose I/O) ports allow direct control and monitoring of peripherals.

The performance of the Diamond 212GP is extremely high: 672 MHz in a 65gp process. It is capable of handling many control plane and DSP applications because of the built-in 32x32 multiplier and 32-bit integer divider.

Get the 2-page Diamond Standard 212GP product brief.

Block Diagram

Diamond Standard 212GP Controller