Diamond 106Micro Product Brief
Diamond Software Tools Product Brief
10 Tips for Successful SOC Design
Xtensa Architecture White Paper
The Diamond Standard 108Mini CPU is a fully synthesizable 32-bit RISC CPU controller core. It is a small, cache-less RISC controller with tightly-coupled local instruction and data memories, a rich interrupt architecture, and high arithmetic and DSP performance. It enables SOC architects to integrate an efficient CPU in their designs, with the added benefit of extremely quick time-to-market. The Diamond 108Mini features class-leading low-power consumption for portable applications.
Although the Diamond 108Mini is smaller in die area than comparable 32-bit CPUs, its performance is extremely high: 420 MHz in a 90nm G process and achieving 1.34 Dhrystone MIPS/MHz. It also achieves high performance on DSP applications and engine and motor control applications because of the built-in 32x32 multiplier and 32-bit integer divider.
The Diamond 108Mini delivers fast and flexible interrupt handling with the availability of low interrupt latency and a rich interrupt architecture. The processor has deterministic behavior for applications with hard real-time constraints. 32 base registers are windowed 16 at a time, which enables much faster context switching due to reduced stack operations. Local single-cycle SRAM allows time critical code to be placed near the CPU. Dual local data SRAM enables processor access to one bank of RAM while an external DNA operation can operate on the other bank. Separate instruction and data memory interfaces lead to lower contention than unified interface architectures.
While small and low power, the Diamond 108Mini achieves the performance levels of much larger, complex CPUs.
Get the 2-page Diamond Standard 108Mini product brief.
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90G
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65GP
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65LP
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| Speed Opt |
Area |
Speed Opt | Area Opt |
Speed Opt
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Area Opt
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Area (mm2) post-synthesis
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0.29 | 0.24 | 0.18 | 0.135 |
0.163
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0.125
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Area (mm2) post-layout
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0.36 | 0.26 | 0.247 | 0.143 |
0.22
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0.138
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Freq (MHz) post-layout
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420 | N/A | 615 | N/A |
360
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N/A
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Power (mW/MHz) post-layout
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0.076 | 0.062 | 0.065 | 0.041 | 0.08 | 0.064 |
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Simulated Leakage (mW)
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0.710 | 0.370 | 1.353 | 0.408 |
0.014
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0.0055
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90G is with TSMC Sage-X libraries.
65GP is with TSMC Advantage library, Regular Vt.
65LP is with TSMC library (Synopsys), Regular Vt.
Area and frequency at worst operating condition (0.9 * Vdd, 125 C)
Power at typical operating condition (1.0 * Vdd, 25 C)
All area and speed calculations are made assuming 8KB local SRAM size
All area, power, and frequency numbers are representative only, and subject to variation based on each user's chosen process technology, cell library, and design tools.

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