The XTensa Modeling Protocol (XTMP) and XTensa SystemC Modeling (XTSC) for Fast
System-Modeling and Simulation Environment
As system design becomes more complex, new methods
to describe, debug, and profile overall system
performance need to be employed. Tensilica’s
XTensa Modeling Protocol (XTMP) and XTensa System C (XTSC) Modeling define a system-level
simulation environment and the application programming
interface (API) to the Xtensa ISS and TurboXim. This allows
one or more Xtensa processors to be simultaneously
running within a system level simulation, a true
multi-processor environment.
XTMP is used for C/C++ models; XTSC is used for SystemC models.
XTMP and XTSC also allow memory modeling of both local
and system memory. System memory can have programmable
latencies specified for different transactions
types, allowing an accurate system simulation for
analyzing performance tradeoffs. Memory-mapped
peripherals may also be included in an XTMP system
simulation, and functions are provided to build
the CPU to user peripheral device transaction interface.
An XMTP or XTSC simulation runs in a multi-threaded environment,
with each processor running in its own thread.
A separate debugger is connected to each core for
full visibility, and core threads can be run asynchronously
or synchronized through events. Another option
is to run all cores in lock-step cycle-by-cycle
mode, if one core stops on a break, all cores stop
until it resumes. XTMP has an extremely wide variety
of options for implementing, controlling, and displaying
results of system simulations deploying multiple
cores, memories, and user-defined devices.
XTMP and XTSC are very flexible, powerful simulation
environments for high-level system design. Both can be used with Tensilica's ISS and TurboXim.
Using the Xtensa ISS and TurboXim with the
XTMP or XTSC Environment in Your SOC Design:
| Code
profiling & Developing TIE Extensions |
Use
the ISS and profiler with the other Xtensa
software development tools to identity “hot
spots” in C code. Iterate through various
Xtensa configurations to tune the processor |
| System
Modeling & Exploration using ISS with XTMP or XTSC |
Use
the Xtensa ISS alone or create a multiple heterogeneous
Xtensa processor simulation using XTMP or XTSC to model
your SOC performance. Experiment with different
hardware & software partitioning across
one, two, ten or more homogeneous or heterogeneous
Xtensa processors in one SOC. |
| System
Modeling with C/C++ environments |
The
Xtensa ISS and XTMP simulators are C-callable
executable programs that can be integrated
into larger SOC |
| System Modeling with SystemC environments |
The Xtensa ISS and XTSC simulators use SytemC. |
| Hardware – Software
CoVerification / Co-Simulation |
The
Xtensa ISS is integrated into the Xtensa CSM
(co-simulation model) for hardware-software
co-design and verification. The Xtensa CSM
is supported by Mentor’s Seamless CVE. |
| TIE
Instruction Verification and Regression Testing |
Tensilica
automatically builds a verification environment
for your designer-defined instruction extensions.
This environment incorporates the ISS and the
processor hardware RTL into a self-checking
testbench that allows the designer to run and
verify the application’s C code and to
exercise the designer-defined TIE instructions. |
|
