Xtensa Instruction Set Simulator (ISS)
and TurboXim Fast Functional Simulator

Tensilica offers two simulators: the Xtensa ISS and the TurboXim fast-functional simulator.

Xtensa ISS

The dynamically configurable Xtensa ISS enables you to analyze, debug and tune the performance of application software before committing the design to silicon. The ISS is a component of the Xtensa software tools suite and is used with the accompanying profiling tools for application tuning and processor configuration.

The ISS is an instruction-count and pipeline accurate model of a configured Xtensa processor, customized to model all TIE instructions by the TIE Compiler for early exploration and by the Xtensa Processor Generator with the final processor RTL. It includes all configurable options and designer defined TIE instructions. The model can be used in system simulations written in C/C++ and System C transaction-level modeling. The ISS lets you know in advance the processor performance
capabilities before you finalize your Xtensa processor design before the SOC design goes out for fabrication.

The ISS can provide cycle counts and performance summary information. It can also generate memory and execution trces, as well as the target program profiling data. Comparisons of profiles from different Xtensa configurations can help you select an optimal set of configuration options.

The ISS also includes a command-loop mode that provides sophisticated, interactive, low-level access to the simulator. The standalone command-loop mode allows cycle- and instruction-stepping, breakpoints, watchpoints, and access to all simulator states, including states introduced by custom instructions created with the Tensilica Instruction Extension (TIE) language.

TurboXim - Fast Functional Simulator

The optional TurboXim fast functional simulator simulates the instruction set of designer-customized Xtensa processors. By using native-compiled code techniques, TurboXim achieves speeds that are 40 to 80 times faster than the cycle-accurate ISS. The TurboXim simulator delivers a peak performance of over 180 million cycles per second on highly iterative code (such as a matrix multiplication DSP kernel), a sustained 50 million simulation cycles per second on complex code running on a typical Xtensa processor, and a sustained 25 million cycles per second on more complex simulations, such as simulating an AAC (Advanced Audio Coding) audio decoder on a VLIW (Very Large Instruction Word) audio DSP processor configuration (like the HiFi2 Audio Engine). [Note that these simulator speeds are cited for single-core simulations running on a Linux workstation with a 3 GHz Opteron 256 processor. Simulation speed varies with the choice of host CPU, system model, and code set.]

The TurboXim simulator enables SOC designers and software developers to simulate Xtensa processor software at speeds similar to an FPGA prototype or emulation environment and at a meaningful fraction of the speed that the processor will run in the actual target SOC. The TurboXim simulator, therefore, is extremely useful for software development and functional verification.

When coupled with XTSC or XTMP models of Xtensa processors, a SOC designer can create a system model of an entire chip or SOC subsystem and perform fast functional verification, as well as provide a very efficient software development environment.

Designers also can perform hybrid simulations using the TurboXim simulator and the ISS. In a hybrid simulation, an application developer can choose to simulate different parts of the same application using either simulator and dynamically switch between them. This allows the designers to collect statistical profiling information of the entire application or detailed profiling information for only the most important parts of the application.

TurboXim gives a much faster simulation than the ISS.

Hybrid Simulations

Tensilica anticipates most customers will also perform hybrid simulations using TurboXim and its ISS. In a hybrid simulation, an application developer can choose to simulate different parts of the same application using either simulator and dynamically switch between them. This allows the designers to collect statistical profiling information of the entire application or detailed profiling information for only the most important parts of the application.

Used with XTMP or XTSC

XTMP is a very flexible, powerful C/C++ simulation environment for high-level system design. XTSC is similar to XTMP, but compatible with SystemC.