The Real Power of Tensilica's Processors - TIE

While you can select from a large number of check-box configuration options when configuring your Xtensa processor, the real power of Tensilica’s Xtensa design environment comes from the use of TIE instructions. TIE (Tensilica Instruction Extension language) “bridges the gap” between the software and hardware design realms, as it is a hybrid of C and Verilog and very easy to learn. TIE lets you add new processor functionality in the form of instructions, execution units, wide load-store instructions, designer-defined I/O interfaces, and designer-defined register files and state registers – all without the need to modify (and then verify) the processor RTL.

TIE allows developers to extend Tensilica’s Xtensa 32-bit microprocessor architecture for specific applications. TIE is optimized for high-level specification of new datapath functions in the form of added instructions and registers. A TIE description is both simpler and much more concise than RTL because it omits all sequential logic descriptions, including FSM descriptions, and initialization sequences. These complex items are actually—and more easily—developed in firmware.

The new instructions and registers described in TIE are available to the firmware programmer via the same compiler and assembler that target the foundation processor’s instructions and register set. Firmware controls the operation sequencing within the datapath extensions through the processor core’s existing instruction-fetch, -decode, and execution mechanisms. Because the instruction extensions greatly accelerate the processor core’s performance on the targeted algorithm, FSM firmware can usually be written in a high-level language (C or C++).

Adding TIE instructions to a Tensilica processor core never compromises the underlying base Xtensa instruction set, thereby ensuring availability of a robust ecosystem of third party application software and development tools. All configurable, extensible Xtensa processors are always compatible with major operating systems, debug probes and ICE solutions; and always come with an automatically generated, complete software development toolchain including an advanced integrated development environment based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry-standard GNU toolchain.

The TIE Compiler is a tool that you use during the development of custom processor hardware extensions. The TIE Compiler also updates the compiler tool chain (XCC compiler, assembler, debugger, profiler) and the simulation models (instruction sets imulator (ISS) and the XTMP system modeling environment) so they understand and fully utilize these new functions. Additionally, TIE RTL and synthesis scripts are produced, which allow you to precisely determine silicon area and maximum frequency of your custom processor extensions.

Software Tool Chain Support for TIE Hardware

Tensilica’s tools take a functional description written in TIE and generate updated processor RTL and software tools to incorporate the new units and instructions.

TIE Development Flow

This means that the designer can now call TIE instructions in C/C++ code as intrinsics and the compiler will schedule these instructions, allocate the designer-defined registers, generate loads and stores for the designer-defined registers, moves between different register files to perform data type conversions, and so on. The debugger will display the designer-defined registers and register files and the internal wires in the TIE functional units. Also, the instruction set simulator will simulate the new instructions in a cycle and pipeline accurate manner. Similarly, the designer can use the RTL generated by the TIE compiler to get a quick post-synthesis estimate of the timing and area of the TIE instructions.

TIE Development Flow:Generate Processor RTL in One Hour

You use the TIE Compiler on your local workstation/PC to iterate in minutes to determine the best instructions for the performance you need combined with any area and power considerations. Once you’ve determined the optimal TIE instructions for your application, that TIE file becomes input for the Xtensa Processor Generator. The Processor Generator automatically produces the entire processor RTL, including the base processor with all configuration options and all TIE extensions.

Describe and Verify Functionality - Not RTL

Since Tensilica’s tools automatically generate pre-verified RTL for the processor that incorporates the units, registers, and instructions specified in TIE, the designer can focus on describing the functionality of the execution unit or instruction they want to design, instead of writing and verifying the RTL. The designer only has to verify the functionality as specified in TIE and not the processor RTL.

Find out how easy it is to create TIE instructions.