Manage Memory Maps and Debug Multiple Cores
Xtensa Xplorer includes chip-level design tools
for multiple-core SOCs. These tools help manage
system memory maps and link/load for multiple-core
SOCs.
The following picture shows the mapping of the
logical address ranges of two different cores in
an SOC to the actual physical memory resources
on the chip.
 Designers
can develop, run and debug multiple-core simulations
using Xtensa
Modeling Protocol (XTMP).
This window shows the placement of code and data
segments within the memory map of the system, showing
both a global as well as a per-processor view.
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