Configure Processors for Your Application
You don't need to be locked into a set of features that were predetermined years of decades earlier by a processor designer. You can configure your Xtensa processor to exactly match your application.
Not sure exactly what options you need? You can use our Xtensa Xplorer IDE to evaluate trade-offs. This section explains some of the tools we have that can help you make intelligent decisions about options such as memory types and sizes, interface options and other execution unit and ISA options.
Configurability of a Tensilica processor core never compromises the underlying base Xtensa instruction set, thereby ensuring availability of a robust ecosystem of third party application software and development tools. All configurable, extensible Xtensa processors are always compatible with major operating systems, debug probes and ICE solutions; and always come with an automatically generated, complete software development toolchain including an advanced integrated development environment based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry-standard GNU toolchain.
Check Box Configuration Options
It's as easy as checking a box to pick the options for your application. The
Xtensa Processor Generator allows quick configuration
of many Xtensa core options using simple clock-box screens, including:
Execution Unit and ISA Options
Sample ISA Configuration Screen Shot
Interface Options
- Processor interface (PIF)
- Width: 32/64/128-bit
- Optional “no PIF” configuration
- Inbound DMA option
- XLMI high-speed local interface
- Choice of 1 or 2 general purpose load/store
units
- Enables classic X-Y style DSP configurations
- Big-Endian/Little-Endian byte ordering
- On-chip debug port
- Trace port signals
- Up to 32 interrupts
- Designer-defined Queues (FIFO interfaces), Ports (GPIOs) and Lookups
- AMBA 3 AXI bridge or AMBA 2 AHB-lite bridge
Memory Subsystem Options
- Memory management options include region protection, region protection with translation, and Memory Management Unit (MMU) with Translation Loo k Aside Buffers (TLBs), including no-execute bit security support for the Linux operating system. See Tensilica's open-source Linux website.
- Local Data and Instruction Caches
- Up to 4-way set associative
- Up to 32 KB
- Write-back and write-through cache write policy
- Separate local RAM, ROM areas for data, instructions
up to 256Kbytes each
- Independent interface widths for all local memories and system bus
- Optional parity or Error Correcting Code (ECC)
Sample Memory Screen Configuration Shot
Design Support
See how Tensilica makes sure your configuration options are properly integrated into your Xtensa processor.
Extra Xtensa LX2 Configuration Options
There are several extra configuration options available only on Xtensa LX2. One is the Vectra DSP engine and another is the HiFi 2 Audio Engine.
Tensilica's Flexible Length Instruction eXtensions (FLIX) is a configuration option that allows designer-defined instructions to consist of multiple, independent operations bundled into a 32-bit or 64-bit instruction word. Read more.
Additionally, Xtensa LX2 allows the use of TIE port (GPIOs) and queues (FIFOs) for greatly expanded bandwidth. Read more.
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