Highly Configurable Base Processor Feature Set
Designers can use the XPRES Compiler to automatically
generate optimized processor extensions. Optionally,
designers can create their own TIE instructions
and edit the results of the XPRES Compiler. The
Xtensa Processor Generator allows quick configuration
of many Xtensa LX core preconfigured options using simple clock-box screens, including:
Execution Unit and ISA Options
Sample ISA Configuration Screen Shot
Interface Options
- Processor interface (PIF)
- Width: 32/64/128-bit
- Optional “no PIF” configuration
- Inbound DMA option
- XLMI high-speed local interface
- Choice of 1 or 2 general purpose load/store
units
- Enables classic X-Y style DSP configurations
- Big-Endian/Little-Endian byte ordering
- On-chip debug port
- Trace port signals
- Up to 32 interrupts
- Designer-defined Queues (FIFO interfaces), Ports (GPIOs) and Lookups
- AMBA 3 AXI bridge or AMBA 2 AHB-lite bridge
Memory Subsystem Options
- Memory management options include region protection, region protection with translation, and Memory Management Unit (MMU) with Translation Loo k Aside Buffers (TLBs), including no-execute bit security support for the Linux operating system. See Tensilica's open-source Linux website.
- Local Data and Instruction Caches
- Up to 4-way set associative
- Up to 32 KB
- Write-back and write-through cache write policy
- Separate local RAM, ROM areas for data, instructions
up to 256Kbytes each
- Independent interface widths for all local memories and system bus
- Optional parity or Error Correcting Code (ECC)
Sample Memory Screen Configuration Shot
HiFi 2 Audio Engine
The popular Xtensa HiFi 2 Audio Engine is a click box option on the Xtensa LX2 processor.
Design Support
Configurability of a Tensilica processor core never compromises the underlying base Xtensa instruction set, thereby ensuring availability of a robust ecosystem of third party application software and development tools. All configurable, extensible Xtensa processors are always compatible with major operating systems, debug probes and ICE solutions; and always come with an automatically generated, complete software development toolchain including an advanced integrated development environment based on the ECLIPSE framework, a world-class compiler, a cycle-accurate SystemC-compatible instruction set simulator, and the full industry-standard GNU toolchain.
|
