HiFi 2 Audio DSP Product Brief
330HIFi Audio DSP Product Brief
388VDO Video DSP Product Brief
Everything You Wanted to Know About Blu-ray Audio, but were afraid to hear
Put Low-Power, Low-Overhead, High-Fidelity Digital Sound in Your Next ASIC or SOC
A Designer's Guide to HD Video Pre- and Post-Processing
How to Add Low-Power, Multi-Codec Digital Video and Audio to Your Next ASIC or SOC Design
If you don't need to further optimize your core and just want a drop-in solution, the 330HiFi is for you. If you want to further optimize your core, use the Xtensa LX2 processor core and click on the HiFi 2 option in the configuration menu.
The 330HiFi core is optimized for digital audio processing. Over 50 popular audio codecs have been pre-ported to the 330HiFi core, which makes it a “drop-in" block for any SOC application requiring high quality, 24-bit audio capability.
Specialized audio instructions designed into the 330HiFi by Tensilica increase code density (reducing memory requirements) and reduce Mhz requirements (lowering power). Techniques used to define these custom instructions include Single Instruction, Multiple Data (SIMD - parallelization), VLIW (multiple operations per cycle), and flexible data path widths (optimum data widths to reduce power).
All of these advanced processor techniques are pre-built into the 330HiFi hardware, and the codecs supplied by Tensilica utilize this hardware to produce the most efficient programmable audio engine available for licensing.
Also, because it's a processor:
The following audio packages are available for the HiFi 2 Audio Engine:
The following voice packages are available for the HiFi 2 Audio Engine:
Because the Xtensa HiFi 2 Audio Engine and 330 HiFi are programmable, multiple standards can run on the same hardware, allowing the same device to play or record digital audio in different standards.
Get the 2-page Diamond Standard 330HiFi product brief.
Get the HiFi 2 Audio Engine product brief for information on all of the codecs available.
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90G
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65GP
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65LP
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Speed Optimized
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Area
Optimized |
Speed Optimized
|
Area
Optimized |
Speed Optimized
|
Area Optimized |
|
|
Area (mm2) post-synthesis
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0.64
|
0.53
|
0.41
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0.31
|
0.35
|
0.28
|
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Area (mm2) post-layout
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0.82
|
0.60
|
0.57
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0.34
|
0.48
|
0.32
|
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Freq (MHz) post-layout
|
351
|
56
|
538
|
57
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312 |
58
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Power (mW/MHz) post-layout
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0.18
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0.15
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0.17
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0.10
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0.19
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0.15
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Simulated Leakage (mW)
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1.68
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0.88
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3.17
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1.04
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0.03
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0.01
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130G and 90G are with TSMC Sage-X libraries.
65GP is with TSMC Advantage library, Regular Vt.
65LP is with TSMC library (Synopsys), Regular Vt.
Area and frequency at worst operating condition (0.9 * Vdd, 132 C)
Power at typical operating condition (1.0 * Vdd, 25 C)
All area and speed calculations are made assuming 8KB local SRAM size
All area, power, and frequency numbers are representative only, and subject to variation based on each user's chosen process technology, cell library, and design tools.
All EDA numbers are for Sage-X libraries. Frequency and power are at worst corner. All area, power, and frequency numbers are representative only, and subject to variation based on each user's chosen process technology, cell library, and design tools. See white paper: Processor Core Power Specs: A Cautionary Tale. Includes VLD (variable length decode).
