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Accelerating C Code, No Assembly Required

Accelerating Existing C Code Using TIE

One of the reasons for resorting to assembly language use is because conventional, fixed-ISA processors often cannot achieve performance goals using C or C++ alone. However, even assembly code is limited to the native performance of the fixed-ISA processor. Tensilica’s Xtensa processor is extensible. This extensibility allows the processor’s resources and capabilities to be tailored to specific tasks. Program optimization using TIE (Tensilica’s Instruction Extension language for the Xtensa processor) is first accomplished by identifying hot spots in the C code – performance-sensitive regions of application code usually residing in the inner loops of algorithms. The execution profiler allows a system designer to quickly analyze code efficiency and to identify where custom instructions (implemented with TIE) can best enhance performance. The software /firmware team or the system designer then defines and implements one or more new TIE instructions to accelerate the hot-spot code.

Stay in C, No Assembly Coding Required

The new TIE instructions appear as intrinsic function calls in C-code routines. The need for assembly coding disappears. Xtensa compilers automatically perform all the necessary optimizations, register allocations, and scheduling of the assembly code generated by the compilation. To get more performance, the system designer can rebuild the processor with additional TIE instructions and re-profile the application to see the performance gain.

The designer can iteratively develop a sequence of processor builds while profiling each new tailored processor to weigh the benefit of adding instructions and pipeline-acceleration hardware through the TIE language. Aggressive use of function-unit parallelism and other acceleration techniques (such as overlapping loads with instruction execution) can often deliver 10X, 100X, or even greater performance increases.

For general information on Xtensa software development tools, click here

For more information on specific software development tools available for the Xtensa processor, click on the links below:

PRODUCT RESOURCES
Xtensa 7 Product Brief
Xtensa Processor Developer's Toolkit Product Brief
  Microprocessor Report's Update on Xtensa LX2 and Xtensa 7
  Epson printer
WHITE PAPERS
Configurable Processors: What, Why, How?
Catching Up with Moore’s Law: How to Exploit the Benefits of Nanometer Silicon
ARTICLES
Reducing SOC Simulation and Development Time
How to Improve ROI in SOC Designs
Automated Verification of Configurable IP Blocks
MPEG-4 is Accelerated with Xtensa V
How Tensilica Verifies Processor Cores
QUOTABLE

“We were faced with lengthening RTL (register transfer level) hardware design cycles. By using Xtensa processors, we cut the design time significantly, plus benefit from the programmability of the solution.”

Dr. Jong-Seok Park,
Vice President of LG.

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