Technical Publications Utilizing Tensilica's Technology

Ecole Polytechnique de Montreal, QC, Canada

Publications

• "A System Level Exploration Platform and Methodology for Network Applications Based on Configurable Processors"
  By Quinn, D., Lavigueur, B., Bois, G., Aboulhamid, M. (2004)
  Proceedings. Design, Automation and Test in Europe Conference and Exhibition, v. 1, p. 364-369.
  
  Dr. Bois' Publications
  
  

National University of Singapore

Publications

• “Instruction-Set Customization for Real-Time Systems”
  Huynh Phung Huynh and Tulika Mitra
  Design Automation and Test in Europe (DATE), April 2007
  
  
• “Characterizing Embedded Applications for Instruction-Set Extensible Processors”
  Pan Yu and Tulika Mitra
  41st ACM/IEEE Design Automation Conference (DAC), June 2004
  
  
• “Satisfying Real-Time Constraints with Custom Instructions”
  Pan Yu and Tulika Mitra
  ACM International Conference on Hardware/Software Codesign and System Synthesis (CODES+ISSS), September 2005
  
  
• “Scalable Custom Instructions Custom Instructions Identification for Instruction-Set Extensible Processors”
  Pan Yu and Tulika Mitra
  ACM/IEEE International Conference on Compilers, Architecture, and Synthesis for Embedded Systems (CASES), September 2004
  
  
• “Handling Constraints in Multi objective GA for Embedded System Design”
  Biman Chakraborty, Ting Chen, Tulika Mitra, Abhik Roychoudhury
  IEEE 19th International Conference on VLSI Design (VLSI), January 2006
  

Princeton University

Publicatons

Princeton Xtensa-related papers

F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, "Custom instruction synthesis for extensible processor platforms," IEEE Trans. on
Computer-Aided Design, vol. 23, Feb. 2004.

Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, "A hybrid energy
estimation technique for extensible processors," IEEE Trans. on
Computer-Aided Design, vol. 23, May 2004.

F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, "Application-specific heterogeneous multiprocessor synthesis using extensible processors," IEEE Trans. on Computer-Aided Design, vol. 25, Sept. 2006.

F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, "A scalable
synthesis methodology for application-specific processors",
IEEE Transactions on VLSI Systems, vol. 14, Nov. 2006.

F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, "A synthesis
methodology for hybrid custom instruction and co-processor generation for extensible processors," accepted for publication in IEEE Trans. on Computer-Aided Design.

N. Aaraj, S. Ravi, A. Raghunathan, and N. K. Jha, "Hybrid
architectures for efficient and accurate face authentication in
embedded systems," IEEE Transactions on VLSI Systems, vol. 15, Mar. 2007.

N. R. Potlapally, S. Ravi, A. Raghunathan, R. B. Lee and N. K.
Jha, "Configuration and extension of embedded processors to optimize IPSec protocol execution," IEEE Trans. on VLSI Systems, vol. 15, May 2007.

D. Arora, A. Raghunathan, S. Ravi, and N. K. Jha, "Architectural support for safe software execution on embedded processors," in Proc. IEEE/ACM International Conference on Hardware/Software Co-Design and System Synthesis, Oct. 2006
(Best Paper Award).

Seoul National University

Publications

• "Instruction Set Synthesis with Efficient Instruction Encoding for Configurable Processors"
  Kiyoung Choi, Nikil D. Dutt, Jong-Eun Lee
• "Buffer Memory Optimization for Video Codec Application Modeled in Simulink"
  Soo-lk Chae, Ahmed A. Jerraya, Sang-ll Han

Stanford University

Publications

• "Comparing Memory Systems for Chip Microprocessors"
  Alex Solomatnikov, Amin Firoozshahian, Jacob Leverich, Hideho Arakida, Mark Horowitz, and Christos Kozyrakis
  Computer Systems Laboratory
  Stanford University
  ISCA '07
  San Diego, CA, USA
  2007
  

• "Chip Multi-Processor Generator"
  Alex Solomatnikov, Amin Firoozshhian, Wajahat Qadeer, Ofer Shacham, Kyle Kelley, Azin Asgar, Megan Wachs, Rehan Hameed, Mark Horowitz
  Stanford University
  DAC 2007
  San Diego, CA, USA
  2007
  

• "Microprocessor Device Takes on FPGAs"
  Nick Flaherty
  Electronics Weekly
  June 21, 2007

TIMA Laboratory

Publications

• "Buffer Memory Optimization for Video Codec Application Modeled in Simulink"
  Soo-lk Chae, Ahmed A. Jerraya, Sang-ll Han
• Programming Models and HW-SW Interfaces Abstraction for Multi-Processor SoC
  By Ahmed A. Jerraya, Aimen Bouchhima, Frederic Petrot

University of California - Irvine

Publication

• "Instruction Set Synthesis with Efficient Instruction Encoding for Configurable Processors"
  By Nikil D. Dutt, Kiyoung Choi, Jong-Eun Lee

University of Adelaide

Publication

"An RNS-Enhanced Microprocessor Implementation of Public Key Cryptography"
41st Asilomar Conference on Signals, Systems and Computers
November 2007

Dr. Braden Phillips
Lecturer
Braden.Phillips@adelaide.edu.au

Zhining Lim
PhD Candidate
zlim@eleceng.adelaide.edu.au

University of New South Wales

Publications

• "Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG"
  Seng Lin Shee, Andrea Erdos & Sri Parameswaran
  International Journal of Parallel Processing
  2007
• "Design Methodology for Pipelined Heterogeneous Multiprocessor System"
  Seng Lin Shee & Sri Parameswaran
  Design Automation Conference (DAC'07)
  San Diego, CA, USA
  2007
• "Instruction Matching and Modeling"
  Paolo Ienne & Rainer Leupers - Editeurs
  Customizable and Configurable Embedded Processors
  Elseiver 2006
• "Heterogeneous Multiprocessor Implementations for JPEG: A Case Study"
  Seng Lin Shee, Andrea Erdos & Sri Parameswaran
  International Conference on Hardware/Software Codesign and Systems Synthesis (CODES+ISSS'06)
  Seoul, Korea
  2006
• "Battery Aware Instruction Generation for Embedded Processors"
  Newton Cheung, Sri Parameswaran & Joerg Henkel
  Asia South Pacific Design Automation Conference (ASP-DAC'05)
  Shanghai, China
  2005
• "A Quantitative Study and Estimation Models for Extensible Instructions in Embedded Processors"
  Newton Cheung, Sri Parameswaran & Joerg Henkel
  International Conference on Computer Aided Design (ICCAD '04)
  San Jose, CA, USA
  IEEE 2004
• "MINCE: Matching Instructions Using Combinational Equivalence for Extensible Processor"
  Newton Cheung, Sri Parameswaran, Joerg Henkel & Jeremy Chan
  Design, Automation and Test in Europe Conference and Exhibition
  DATE '04 Proceedings
• "Instruction Selection/Identification & Design Exploration for Extensible Processors"
  Newton Cheung, Sri Parameswaran & Joerg Henkel
  International Conference on Computer Aided Design (ICCAD '03)
  San Jose, CA
  IEEE
• "Rapid Configuration & Instruction Selection for an ASIP: A Case Study"
  Newton Cheung, Sri Parameswaran & Joerg Henkel
  Embedded Software for SoC
  Kluwer Publishing
  IEEE
  2003
  
  http://www.cse.unsw.edu.au/~sridevan/pubs/sri.html

University of Ottawa

References and Published Papers

• "Simplifying Physical Realization of Gaussian Particle Filters with Block Level Pipeline Control"
  S. Hong, J. K. Lee, M. Bolic, P. M. Djuric, HYPERLINK
  EURASIP Journal of Applied Signal Processing, No. 4, pp. 575-587, 2004.
  
• "Resampling Algorithms and Architectures for Distributed Particle Filters"
  M. Bolic, P. M. Djuric, S. Hong, HYPERLINK
  IEEE Transactions on Signal Processing, 2004
• "Resampling Algorithms for Particle Filters: A computational Complexity Perspective"
  S. Hong, M. Bolic & P. M. Djuric, HYPERLINK
  EURASIP Journal of Applied Signal Processing, 2004
• "An Efficient Fixed-Point Implementation of Residual Systematic Resampling Scheme for High-Speed Particle Filters"
  S. Hong, M. Bolic, & P. M. Djuric, HYPERLINK
  IEEE Signal Processing Letters, vol. 11, No. 5, May 2004

Submitted Papers

• "A Study of Gaussian Particle Filters for Practical Physical Implementation"
  M. Bolic, A. Athalye, P. M. Djuric, & S. Hong
  Submitted to IEEE Transactions on Circuits and Systems I, 2004
• "Design and Implementation of flexible Resampling Mechanism for High-Speed Parallel Particle Filters"
  S. Hong, S. S. Chin, M. Bolic, & P. M. Djuric
  Submitted to Journal of VLSI Signal Processing, 2003

University of Paris SUD

Publication

• "Customizing 16-Bit Floating Point Instructions on a NIOS II Processor for FPGA Image and Media Processing"
  D. Etiemble, S. Bouaziz and Lionel Lacassagne
  IEEE Workshop on Embedded Systems for Real Time Media Processing (Estimedia), Jersey City, September 2005