Research using Tensilica's Technology

Current Research/Projects

1. The HI-TECH Research and Development Program of China (863) project. "The sharing memory interconnection in MPSoCs (2007AA01Z182).
2. The National Natural Science Foundation of China project. "Dynamically memory distribution using network coding in MPS0cs (60706027).
3. The National Colleges Novelty project. "Digital IF IC design".

Multiprocessors (MPSoCs) architectures are becoming a promising choice in designing of complex embedded systems. There are several reasons for this trend. First, these architectures employ simpler easy-to-verify processors as compared to complex single processor based architectures. This makes them arguably easier to validate and verify. Second, a MPSoCs architecture can be clocked at a reduced speed (again compared to single processor based systems), and this can improve power efficiency. This flexibility is a direct result of having multiple processors on the same die; that is, the performance loss due to reduced clock frequency can be compensated through on-chip parallel processing. Third, these architectures match very well with high level (e.g., loop level) parallelism and this makes them perfect candidates to execute array/loop-intensive embedded applications from different domains. For example, many applications from the domain of embedded multimedia processing are built from a series of nested loops accessing multi-dimensional arrays of signals.

One of the critical components of a MPSoCs based system is its memory hierarchy and interconnection. While circuit level optimizations and architectural issues are very important (e.g., how many levels the memory hierarchy has, whether it is software of hardware managed, what the unit of transfer between memory components is, how inter-processor synchronization is maintained, etc.), equally important are software level optimizations that minimize the execution cycles spent in memory accesses and/or reduce memory energy consumption. Therefore, Tensilica's Xtensa processor may provide us a platform to explore the issues mentioned above, as well as an early step comparison between different techniques, as well as help us reach our research target smoothly and fleetly.

The available resources that we have are out brains and experience in designing digital ASICs using Synopsys, Cadence, Mentor or other EDA tools for many years, meanwhile, our EDA center has more than 50 PCs/workstations and the EDA tools mentioned above.

Outline of Curriculum and Courses

1. Structured Integrated Circuits Design
2. EDA Tools Practices
3. Digital Wireless Signal Processing Simulation of Communication Systems and Design of Communication System-on-Chip
4. Low Power Digital Design

Student/Assistants Outreach

1. 2 teachers
2. 2 PhD candidates in grade three
3. 1 PhD candidate in grade two
4. 3 PhD candidates in grade one
5. 4 master candidates in grade one and two

Prof. Jueping Cai
jpcai@sjtu.org
jpcai@mail.xidian.edu.cn

Xidian University link