Research using Tensilica's Technology

Current Research

The Edward S. Rogers Sr., Department of Electrical and Computer Engineering

Over the past several months, we developed a framework to facilitate automated design space exploration (DSE) of multiprocessor system-on-chips (MPSOCs) built over Tensilica's tools. The framework automates the process of building system configurations, starting and monitoring multiple concurrent simulations of task-parallel applications with real-time requirements, analyzing simulation results and graphically viewing dynamic time and energy execution profile, and generating area vs. energy plots to show pare to-optimal tradeoffs in the design space. Our interactive or script-driven framework makes it easy to maintain information about and navigate through the design space, allowing us to focus more on developing exploration algorithms and experimenting with estimation techniques and new system organization approaches.

We found the automation support available with Tensilica tools (especially the xtsc-run program) very helpful when building this framework. In addition, we are grateful for the detailed and very well-written documentation provided by Tensilica, as well as the generous and prompt support provided through the tensilicausers discussion group.

We are excited to pursue the next step in our research plan: experimenting with different DSE algorithms and high-level estimation techniques to expedite the process of understanding design space tradeoffs for given target application(s). Our goal is to minimize the number of time-consuming cycle-accurate simulations needed to reach an acceptable confidence level in tradeoff results.

In addition, Prof. Jianwen Zhu (also at ECE, University of Toronto) is interested in using Tensilica tools for research. The following is a brief description of Prof. Zhu's motivation and work plan:

There are many competing approaches for application acceleration. The most notable include application-specific instruction set processor, exemplified by Tensilica solution, and behavioral synthesis. while it is well understood that the two approaches make different tradeoffs among performance, cost and flexibility, such tradeoff are not quantified among different family of applications.

Such study is particularly difficult, partly because state-of-the-art behavioral synthesis tools do not scale to large C programs, and impose many restrictions to the styles of C program they can accept.

To cope with the challenge, we take two approaches. In the first approach, we develop a set of benchmarks, and make sure they are developed with common denominator constraints of today's commercial behavioral synthesis tools. In the second approach, we use the standard EEMBC benchmark, as well as a scalable academic behavioral synthesis tool.

The result of this study could potentially help Tensilica's customers make more informed decisions.

University of Toronto

Department of Electrical and Computer Engineering