Princeton University

Prof. Jha is studying a wide range of subjects related to embedded systems, and more information can be found at the embedded systems group web site.

Professor Wolfe has done extensive research on multiple processor system-on-chip (MPSOC) and sponsors a workshop on this subject. Tensilica was a sponsor of the 2006 workshop. He has also published a book on MPSOC design that includes a chapter by Tensilica's president, Chris Rowen.

Research

Our main usage for Tensilica tools, will be for research purposes.

As part of recent and on going work in our research group, the Xtensa platform has been and will be used for different kinds of applications and design methodologies.

Past work includes the use of the Xtensa extensible processor in the design of automation methodologies for custom instruction selections, for synthesis of custom heterogeneous architectures consisting of multiple extensible processors, and for generating a combination of co-processors and custom instructions.

Also, we used the Xtensa platform for designing efficient and secure authentication methods for embedded systems based on robust fingerprints and face authentication algorithms. Our architectural enhancements for embedded systems include complete design and evaluation of custom instructions and single chip multiprocessor (co-processor) systems using Xtensa ISS and Xtensa XTMP environments. Versions of this work were presented at the Design Automation Conference (DAC), 2005, and the Design, Automation, and Test in Europe (DATE) Conference, 2006.

As part of our ongoing research, we are investigating the feasibility of implementing custom instructions for ensuring memory-safety in unsafe C program. We used the CCured framework to produce an instrumented C source file that has memory-safety checks inserted at appropriate program locations. A preliminary version of this work was presented in our paper titled "Architectural support for safe software execution on embedded processors", which received the best paper award at the ACM/IEEE International Conference on Hardware Software Co-design and System Synthesis (CODES+ISSS), 2006. However, the above paper used only single-cycle instructions for memory-safety checks. Next, we would like to investigate the possibility of further speed-up with the use of multi-cycle instructions. We will also, explore the use of wide read/write ports to accelerate some of the checks.

Another aspect of our research is investigation of the resource consumption of a Software-based Trusted Platform Module (SW-TPM) on embedded platforms. A preliminary version of our work, looking into the energy and execution time consumption of the SW-TPM on handheld devices, will be presented at DATE Conference, 2007. Next, we would like to investigate the resource consumption of SW-TPM on an Xtensa platform, and implement custom instructions and multiprocessor systems for accelerating core cryptographic kernels executing in the SW-TPM. Our work will include a complete evaluation of the customized processor(s), and the effectiveness and benefit of our deign will be compared to commercially available TPM chips.

Outline of Curriculum and Courses

• ELE 206 Introduction to Logic Design
• ELE 375 Computer Architecture and Organization
• ELE 402 Digital Electronics
• ELE 461 Design with Nanotechnologies
• ELE 462 Design of Very Large Scale Integrated (VLSI) Systems
• ELE 464 Embedded Computer
• ELE 465 Switching and Sequential Systems
• ELE 475 Computer Architecture
• ELE 563 Electronic Design Automation
• ELE 577 Low Power IC and System Design

Student/Assistants Outreach

The students who will use Tensilica tools are mainly graduate students working towards the completion of their PhD degree. The number of students in our group, working on system-level design methodologies and on the design of efficient and secure architectures for embedded systems is around five at any given time.

Princeton Xtensa-related papers

• F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, "Custom instruction synthesis for extensible processor platforms," IEEE Trans. on
  Computer-Aided Design, vol. 23, Feb. 2004.
• Y. Fei, S. Ravi, A. Raghunathan, and N. K. Jha, "A hybrid energy
  estimation technique for extensible processors," IEEE Trans. on
  Computer-Aided Design, vol. 23, May 2004.
• F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, "Application-specific heterogeneous multiprocessor synthesis using extensible processors," IEEE Trans. on Computer-Aided Design, vol. 25, Sept. 2006.
• F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, "A scalable
  synthesis methodology for application-specific processors",
  IEEE Transactions on VLSI Systems, vol. 14, Nov. 2006.
• F. Sun, S. Ravi, A. Raghunathan, and N. K. Jha, "A synthesis
  methodology for hybrid custom instruction and co-processor generation for extensible processors," accepted for publication in IEEE Trans. on Computer-Aided Design.
• N. Aaraj, S. Ravi, A. Raghunathan, and N. K. Jha, "Hybrid
  architectures for efficient and accurate face authentication in
  embedded systems," IEEE Transactions on VLSI Systems, vol. 15, Mar. 2007.
• N. R. Potlapally, S. Ravi, A. Raghunathan, R. B. Lee and N. K.
  Jha, "Configuration and extension of embedded processors to optimize IPSec protocol execution," IEEE Trans. on VLSI Systems, vol. 15, May 2007.
• D. Arora, A. Raghunathan, S. Ravi, and N. K. Jha, "Architectural support for safe software execution on embedded processors," in Proc. IEEE/ACM International Conference on Hardware/Software Co-Design and System Synthesis, Oct. 2006
  (Best Paper Award).
  

Princeton University's URL link

Princeton University's Electrical Engineering's URL link

Contact Prof. Niraj K Jha
Professor of Electrical Engineering
Home Department: Electrical Engineering
Office Location: B220 Engineering Quad
Voice Mailbox: 84754
E-mail: jha@Princeton.EDU
Homepage
NetID: jha