Research
Project 1
Investigate security in multiprocessor embedded system. This work uses Tensilica Xtensa LX2 processor to build a system with multiple processors. This research work is interested in secure execution of programs running on a multiprocessor embedded system. It uses TIE to extend the base architecture and efficiently implement security checks in the programs running on individual cores. Xtensa Modeling Protocol (XTMP) is then used to connect these processors together into a single system and carry out simulations. The FIFO queues are also extensively used for communication between different cores in the multiprocessor system.
Project 2
The research work introduces a heterogeneous multiprocessor system using ASIPs as processing entities in a pipeline configruation. The problem of mapping each algorithmic stage in the system to an ASIP configuration is formulated. An esitmation technique to calculate runtime of the configured multiprocessor system without running cycle-accurate simulations which may take a significant amount of time was proposed. Heuristics are eveloped to quickly and efficiently explore the design space. The set of configurations obtained are compared against the optimal configurations (obtained via exhaustive search) using cost efficiency metrics. The research uses the Tensilica toolset to generate cores and customized instructions while quicly evaluating the architectures against various cache sizes and multipprocessor configurations using the instruction set simulator and XTMP framework.
Project 3
We use Tensilica Xtensa Tool to design a customized Network Processor which supports Network Intrusion Detection. The system created such that we are able to simulate a monitor and a detector in real time. We generate several cores to communicate wtih each other, and use XTMP to simulate. TIE instructions supported by Tensilica is used to crate a pipelined Network Processor architecture. Between a pair of cores, FIFOs are employed as channels to transfer requested data to next.
"Architectural Exploration of Heterogeneous Multiprocessor Systems for JPEG"
Seng Lin Shee, Andrea Erdos & Sri Parameswaran
International Journal of Parallel Processing
2007
"Design Methodology for Pipelined Heterogeneous Multiprocessor System"
Seng Lin Shee & Sri Parameswaran
Design Automation Conference (DAC'07)
San Diego, CA, USA
2007
"Instruction Matching and Modelling"
Paolo Ienne & Rainer Leupers - Editeurs
Customizable and Configuralbe Embedded Processors
Elseiver 2006
"Heterogeneous Multiprocessor Implementations for JPEG: A Case Study"
Seng Lin Shee, Andrea Erdos & Sri Parameswaran
International Conference on Hardware/Software Codesign and Systems Synthesis (CODES+ISSS'06)
Seoul, Korea
2006
"Battery Aware Instruction Generation for Embedded Processors"
Newton Cheung, Sri Parameswaran & Joerg Henkel
Asia South Pacific Design Automation Conference (ASP-DAC'05)
Shanghai, China
2005
"A Quantitative Study and Estimation Models for Extensible Instructions in Embedded Processors"
Newton Cheung, Sri Parameswaran & Joerg Henkel
International Conference on Computer Aided Design (ICCAD '04)
San Jose, CA, USA
IEEE 2004
"MINCE: Matching Instructions Using Combinational Equivalence for Extensilbe Processor"
Newton Cheung, Sri Parameswaran, Joerg Henkel & Jeremy Chan
Design, Automation and Test in Europe Conference and Exhibition
DATE '04
Proceedings
"Instruction Selecton/Identification & Design Exploration for Extensible Processors"
Newton Cheung, Sri Parameswaran & Joerg Henkel
International Conference on Computer Aided Design (ICCAD '03)
San Jose, CA
IEEE
"Rapid Configruation & Instruction Selection for an ASIP: A Case Study"
Newton Cheung, Sri Parameswaran & Joerg Henkel
Embedded Software for SoC
Kluwer Publishing
IEEE
2003
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