Research using Tensilica's Technology

The following is information about our project executing - "Multi-Pipeline Reconfigurable System" that is supported by National Natural Science Foundation of China.

Our reconfigurable computing project presents a coarse-grained run-time reconfigurable architecture (as the co-processor of a MIPS core processor) that aims at exploiting loop level parallelism in both temporal and spatial dimensions by fitting multiple pipeline into the reconfigurable fabric. Based on the system, we'll present the basic cell and interconnection of the reconfigurable fabric. Also, we'll illustrate how an application is mapped onto and computed by our system and give the supposed co-compiler framework. The core processor (a close derivative of the MIPS architecture, and maybe the Xtensa processor can act as the real core processor) mentioned above is an open C source model developed by University of Wisconsin. Based on this core, we have added new instructions (used for the reconfigurable co-processor operation) to the original MIPS-IV instruction set. In our MPRS system, the co-processor executes the compute-dense operation, such as FIR, convolution, matrix multiplication and other DSP algorithms by run-tim reconfiguration; the core processor executes the control operation.

Y.S. Yin
Institute of VLSI Design
Hefei University of Technology

The Hefei University of Technology's URL link