Research Description

Architecture Exploration of Embedded Systems
By: Ahmed Elhossini, PhD Student
Advances in chip technology have enabled integrating many functional units on a single chip. This led to the emergence of the concept of System-on-Chip (SoC). SoC is the foundation for the development of advanced embedded systems. Embedded systems are widely used today in different Digital Signal Processing (DSP) applications that usually require high computation power and tight constraints. Using SoC technology increases the challenges facing the designer to choose the optimal design. A tool that helps explore different architectures is required to design an efficient system. The tool should be able to explore different architectures and evaluate them according to the given constraints. The design space to be explored depends on the application domain, and the target platform. Reconfigurable devices, such as Field Programmable Gate Arrays (FPGA), have evolved to the extent that a complete DSP application can be implemented on a single device. Due to the variety of architectures and different objectives that constrains the design of SoC embedded systems, Architecture Exploration (AE) could be viewed as a multi-objective optimization problem.
In this research project an architecture exploration framework for the exploration of embedded DSP systems is proposed. In the last stages of this research the use of this framework on top of Tensilica tools perform architecture exploration for systems based on Xtensa processors will be investigated.

Hardware Accelerator for a Maze Routing
By: Mahdi Ghazali, M.Sc. Student
According to Moore’s law the size of a transistor will be reduced every eighteen months [1] and, the complexity of the Integrated Circuits will increase since we will have a larger number of transistors in the chip; nowadays, this number has achieved 1 Billion. As a result, the fabrication process of Very Large Scale Integration (VLSI) becomes a very hard process. Therefore, it is important to create faster techniques to reduce the time that the VLSI physical design automation takes. VLSI physical design automation is the process of converting a specific circuit design into a layout. This process consists of many steps such as partitioning, routing, placement and packaging [2]. Many studies have been done to improve these steps. The goal of my research is to design a hardware accelerator for a maze routing using Tensilica and Xilinx tools.

Outline of Curriculum and Courses

ENG2410 Digital Design
ENG3380 Computer Organization
ENG6090 Reconfigurable Computing Systems
ENG6090 VLSI
ENG6090 Analog IC Design
ENG6560 Advanced Digital Signal Processing

Student/Assistants Outreach

• We expect to have between 10 to 25 graduate students per year who will use Tensilica tools in their research.
• The number of undergraduate students who might use the Tensilica tools will range between 60 to 80 students.
• We are interested in participating in college recruiting programs with Tensilica.

University of Guelph's URL

University of Guelph's School of Engineering URL

University of Guelph's Personal Website for Prof. Shawki Areibi URL