Outline of Research using Tensilica's Technology

Kiyoung Choi
Design Automation Lab
Seoul National University

Research

• Multi-Processor SoC Design from a Process Network System Model
  It is a major trend to put more processors in an SoC for both performance and flexibility. However, limited communication bandwidth of typical processors is the most serious source of performance bottleneck in such a Multi-Processor SoC (MPSoC). The goal of this research is to develop a methodology for a systematic design of an MPSoC starting from a process network model of the target application. It is based on a configurable processor architecture with multiple I/O ports. Tensilica's Xtensa LX is a currently available architecture that fits best with our purpose. In our research, we take video applications such as JPEG, H.263, and H.264. We model the application as a Kahn Process Network (KPN) and partition it into processes running on multiple processor individually configured for their own processes. Each FIFO connection in the original KPN model is mapped to the Queue in the Xtensa LX architecture. The mapping is easy and efficient since we do not need to consider bus arbitration and cycle overhead for the I/O. The research is now in its infant stage and we need much work to show the effectiveness of the approach. However, we think it is viable from many points of view, such as flexibility, performance, and efficiency of the design process.
• Performance Estimation of a Configurable Processor
  Static estimation of software performance has been an important research topic in real-time systems society. It is important in that it guarantees pessimistic estimation of the worst case execution time (WCET). However, there has been no research on applying it to software running on a configurable processor. Tensilica's XPRES compiler estimates the performance dynamically (through simulation) for every configuration of the processor, taking long time, but with no guarantee of obtaining pessimistic estimation. In this research, we apply the well known static estimation techniques to a configurable processor architecture such as Tensilica's Xtensa to explore the architecture configuration space much faster. We have implemented a toy tool and applied it to Xtensa and found that the methodology can be useful for real-time systems design using configurable processors.

Classes

• Embedded Systems Design (420.417)

This course is for senior-level undergraduate students. It covers basics of embedded systems design, including embedded processor architecture, embedded operating systems, hardware components design, and system integration. Several sets of term projects are assigned for hands-on experience.

The Tensilica Xtensa architecture and the development environment have been included in the lecture of embedded processor architecture.

• SoC Design Automation (4541.633A)

This course is for graduate students. We discuss methodologies and tools for designing a system integrated on a chip (SoC: System-on-Chip), which involves both hardware and software. Major issues covered in this course include system specification and modeling, application to architecture mapping, embedded processors, IP integration and on-chip communication, hardware synthesis, software synthesis, low power systems design, real-time systems design, and design validation.

The Tensilica Xtensa architecture and the development environment have been included in the lecture of embedded processors.

Papers

Instruction Set Synthesis with Efficient Instruction Encoding for Configurable Processor
By Kiyoung Choi

Buffer Memory Optimization for Video Codec Application Modeled In Simulink
By Soo-lk Chae