Cadence is a leading EDA vendor offering a variety of excellent tools. Tensilica supports logic simulation with Verilog XL and NC Verilog as well as Cadence’s Silicon Ensemble layout software. Tensilica is collaborating with Cadence to support SOC Encounter.

The Tensilica-Cadence Encounter® RTL-to-GDSII methodology streamlines the development of SoC designs based on the Tensilica’s Diamond Standard processor family. The Diamond Standard processor family includes six cores, ranging from a low-power 32-bit controller to the industry’s highest performance DSP.

The Encounter digital IC design platform integrates global RTL and physical synthesis, high performance SI-aware routing, and sophisticated nanometer analysis and optimization. It is ideal for large scale, low power, yield-sensitive, and other demanding design challenges and is production-proven through the 65nm node.

Tensilica is a member of Cadence’s OpenChoice IP program. The OpenChoice IP program enables IP interoperability, facilitates collaboration, and provides access to leading IP providers for Cadence customers.

See June 2007 Press Release

For a complete list of EDA tools and the EDA tool flow supported by Tensilica, click here.