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October 16, 2007

Tensilica Ports MPEG-4 BSAC Decoder for Digital Multimedia Broadcasting (DMB) to HiFi 2 Audio Engine

 

SANTA CLARA, CA, – October 16, 2007 – Tensilica, Inc. today announced that it has added a MPEG-4 Bit Sliced Arithmetic Coding (BSAC) decoder to Tensilica’s HiFi 2 Audio Engine, the most popular commercial audio core for system-on-chip (SOC) designs. This BSAC decoder is used in Digital Multimedia Broadcasting (DMB) applications, which allow radio, TV and datacasting to mobile devices, particularly mobile phones.

“DMB popularity is on the rise, with popular services in South Korea and Germany, trials in Paris, Norway, Italy, Indonesia, and Ghana, and service plans in China for the 2008 Olympics,” stated Larry Przywara, Tensilica’s director of mobile multimedia. “By providing this decoder, we can save device manufacturers the time and effort of developing the decoder themselves, getting them into volume production quicker.”

MPEG-4 BSAC was standardized by ISO/IEC 14496-3 subpart 4. BSAC replaces the Huffman coding portion of the conventional AAC standard used for noiseless coding of scale factors and spectral data. The rest of the processing is identical to AAC. It offers fine grain audio scalability in the range from 16kbps to 64kbps in steps of 1kbps per audio channel and provides error resilience for greatly improved audio quality of a signal transmitted over an error-prone channel such as a wireless network.

Availability and Specifications


The BSAC decoder for the HiFi 2 Audio Engine also works with Tensilica’s Diamond 330HiFi Audio Processor Core and is available now. Tensilica’s MPEG-4 BSAC decoder requires just 25 MHz at 44.1 kHz, 64 kbps, making it very efficient for portable applications.

About Tensilica


Tensilica, Inc., is the recognized leader in configurable processor technology and has leveraged that technology to become the leading supplier of licensable controllers and DSP cores for mobile audio and video applications. Tensilica offers the broadest line of controller, CPU, network, and specialty DSP processors on the market today – including full software toolchain and modeling support - in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. The modern design behind all of Tensilica’s processor cores provide semiconductor companies and system OEMs with the lowest power, smallest area solutions for high-volume products including mobile phones and other consumer electronics, networking and telecommunications equipment, and computer peripherals. For more information on Tensilica’s patented, benchmark-proven processors, visit www.tensilica.com.

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Editors’ Notes:


  • Tensilica and Xtensa are registered trademarks belonging to Tensilica Inc. All other company and product names mentioned are trademarks and/or registered trademarks of their respective owners.
  • Tensilica’s announced licensees include Afa Technologies, ALPS, Aquantia, Astute Networks, Atheros, AMD (ATI), Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Brocade, Cisco Systems, CMC Microsystems, Conexant Systems, EE Solutions, Epson, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, iBiquity Digital, Ikanos Communications, Intel, Juniper Networks, LG Electronics, Lucid Information Technology, Marvell, NEC Laboratories America, NEC Corporation, NetEffect, Neterion, Nethra Imaging, Nippon Telephone and Telegraph (NTT), NuFront, NVIDIA, Olympus Optical Co. Ltd., Penstar, Plato Networks, PnpNetwork Technologies, Server Engines, SiBEAM, Silicon Optix, Sony, STMicroelectronics, Stretch, TranSwitch Corporation, u-Nav Microelectronics, Validity Sensors, Victor Company of Japan (JVC), and XM Radio.
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“It is faster and easier to design complex SOCs using Xtensa configurable processors - especially when using the XPRES Compiler - than to hand-code complex SOC design elements in hardware using traditional RTL methods. Plus the Xtensa processors are programmable, so it will be valuable for future products and applications.”

- Katsuhiko Nishizawa, general manager of the IJP Design Department of the Imaging Products Operations Division of Seiko Epson Corporation.