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December 4, 2006

Lauterbach’s TRACE32 PowerView Debugger Supports Tensilica’s Diamond Standard and Xtensa Processor Cores

Hofolding, GERMANY, and Santa Clara, Calif. USA – December 1st, 2006 – Lauterbach and Tensilica today announced that Lauterbach now supports Tensilica’s Diamond Standard and Xtensa configurable processors with its TRACE32 PowerView microprocessor debugger. Lauterbach’s debugger speeds software development on Tensilica’s processor cores.

“Over the past year, we’ve seen increasing demand for our products on both families of Tensilica processors – the Diamond Standard series and the Xtensa configurable processors – as more designers are using these products in their SoC designs,” stated Norbert Weiss, International sales manager from Lauterbach. “Tensilica’s processors are particularly popular in multicore designs, which we service very well with our TRACE32-ICD.”

The PowerDebug (in-circuit debugger) is a high-performance JTAG debugger. The PowerDebug’s hardware consists of a universal debug module that can be connected to any PC or workstation via a USB 2.x or Ethernet interface. The PowerView software supports multicore debugging. Graphical variable displays and dedicated commands to handle large arrays support the development of DSP-specific code. The combination of the debugger and the PowerProbe logic analyzer enables real-time measurements. The PowerView debugger software provides a unified, graphical environment for debugging SoCs with one or more Tensilica processors, or a combination of Tensilica processors plus cores from other vendors in a heterogeneous debug environment.

“Lauterbach is well respected as having a premier debugging solution for SoC designs and several of our customers have requested this support, so we’re delighted to offer our customers this resource for their design activity,” stated Larry Przywara, Tensilica’s director of strategic alliances.

Availability

The Lauterbach TRACE32 PowerView and PowerDebug are available now from Lauterbach.

About Tensilica

Tensilica offers the broadest line of controller, CPU and specialty DSP processors on the market today, in both an off-the-shelf format via the Diamond Standard Series cores and with full designer configurability with the Xtensa processor family. Tensilica’s low-power, benchmark proven processors have been designed into high-volume products at industry leaders in the digital consumer, networking and telecommunications markets. All Tensilica processor cores are complete with a matching software development tool environment, portfolio of system simulation models, and hardware implementation tool support. For more information on Tensilica's patented approach to the creation of application-specific building blocks for SOC design, visit www.tensilica.com.

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Editors’ Notes

  • Tensilica and Xtensa are registered trademarks belonging to Tensilica Inc. FLIX and XPRES are trademarks of Tensilica. All other company and product names are trademarks and/or registered trademarks of their respective owners.
  • Tensilica’s announced licensees include Afa Technologies, ALPS, AMCC (JNI Corporation), Aquantia, Astute Networks, Atheros, ATI, Avago Technologies, Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, Cypress, Crimson Microsystems, EE Solutions, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, Hughes Network Systems, iBiquity Digital, Ikanos Communications, LG Electronics, Lucid Information Technology, Marvell, MediaWorks, NEC Laboratories America, NEC Corporation, NetEffect, Neterion, Nethra Imaging, Nippon Telephone and Telegraph (NTT), NuFront, NVIDIA, Olympus Optical Co. Ltd., PnpNetwork Technologies, sci-worx, Seiko Epson, Solid State Systems, Sony, STMicroelectronics, Stretch, TranSwitch Corporation, u-Nav Microelectronics, Victor Company of Japan (JVC) and WiQuest Communications.
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“It is faster and easier to design complex SOCs using Xtensa configurable processors - especially when using the XPRES Compiler - than to hand-code complex SOC design elements in hardware using traditional RTL methods. Plus the Xtensa processors are programmable, so it will be valuable for future products and applications.”

- Katsuhiko Nishizawa, general manager of the IJP Design Department of the Imaging Products Operations Division of Seiko Epson Corporation.