Tensilica Optimizes Methodology for 90-nm Design
Flow
Latest Synopsys and Cadence Tools Supported
Santa Clara, Calif. – August 29,
2005 – Tensilica®,
Inc., today announced that it has enhanced its
automated configurable processor design methodology
to account for common integrated circuit design
challenges with 90-nanometer (nm) process technology.
These enhancements support the latest capabilities
of the Cadence® and Synopsys® tools
and include automated generation of physical design
flow scripts that significantly lower power consumption,
automate the input of user-defined power structures,
and support crosstalk analysis.
“90 nanometer design presents significant
new challenges for IC designers,” stated
Steve Roddy, Tensilica’s vice president of
marketing. “By automating the script development
for the best-in-class design tools, we can speed
our customers’ designs to market.”
Meeting 90-nm Challenges
One of the big challenges of 90nm silicon is that dynamic power consumption rises dramatically. Tensilica counters this by automating the insertion of fine-grain clock gating throughout the Xtensa LX core and all designer-defined extensions. Synopsys' Power Compiler T is used for further power optimizations.
Another 90-nm silicon challenge is the increased
severity of IR drop across power rails. New automatically
generated Xtensa layout scripts automate the input
of designer-defined power structure into the layout
tools.
Interconnect parasitic effects are the third 90-nm
challenge. Interconnects, which have dominated
signal delay in all submicron technologies, are
now critically affected by layout parasitic effects.
Therefore, interconnect modeling accuracy is a
critical input. New automatically generated Xtensa
layout scripts also automate electrical parameter
input from tool-specific technology files to better
model parasitic effects.
Crosstalk avoidance and clock skew/insertion are
critical design requirements for 90-nm designs.
Tensilica’s new scripts automatically support
Cadence’s CeltIC® for crosstalk analysis.
Tensilica’s new scripts enable “useful
skew modes” in the Synopsys Astro™ and
Cadence SOC Encounter™ place and route tools
to deliver maximum achievable clock rates.
Support for New Synopsys and Cadence Tools
Tensilica
has worked closely with Synopsys and Cadence
to support their new generation of 90nm design
tools. The following Synopsys Galaxy™ Design
Platform and Cadence tools are fully supported
by Tensilica’s design methodologies:
| IC Design Step |
Tool Supported |
| Logic synthesis |
Synopsys Design Compiler®, Synopsys Power
Compiler |
| Physical Implementation |
Synopsys Physical Compiler®, Synopsys
Astro, Cadence SOC Encounter, Cadence NanoRoute™ |
| RC extraction |
Cadence Fire & Ice® QX |
| Timing sign off |
Synopsys PrimeTime |
| Signal integrity analysis |
Cadence CeltIC |
| Design for Test |
Synopsys DFT Compiler, Synopsys TetraMAX ® ATPG |
Tensilica has automated the production of synthesis
and implementation scripts for Xtensa processors.
These scripts are automatically generated for every
Xtensa V and Xtensa LX processor configuration.
The Xtensa hierarchy is fully understood by these
scripts and the scripts include full support for
designer-defined TIE (Tensilica Instruction Extensions)
language extensions to the base processors.
The automated scripts even support custom instructions
that require more than one clock cycle to complete.
Logic dependencies are grouped automatically so
the logic hierarchy is re-organized for timing
optimization. Tensilica uses a bottoms-up approach
with multiple passes on the top level to produce
scripts that require no additional user modification.
Advanced SOC designers, however, are free to modify
and extend these scripts to meet company-specific
physical design rules or goals.
“Cadence Encounter tools have helped Tensilica
to streamline the 90 nanometer design flow with
the automatic generation of scripts,” said
Eric Filseth, vice president of product marketing
for Cadence Digital Implementation group. “This
will enable our mutual customers to achieve a fast,
efficient path to silicon for their application
optimized Xtensa-based designs.”
“Tensilica understands and has worked with
Synopsys to address the challenges poised by 90
nanometer technologies,” said Lonn Fiance,
director of Strategic Alliances, Synopsys. “Linking
the 90 nanometer proven Synopsys Galaxy Design
Platform with Tensilica’s automatically generated
synthesis and implementation scripts provide a
faster path for Tensilica’s customers to
design customized processors in leading edge processes.”
About Tensilica
Tensilica was founded in July 1997 to address
the growing need for optimized, application-specific
microprocessor solutions in high-volume embedded
applications. With a configurable and extensible
microprocessor core called Xtensa, Tensilica is
the only company that has automated and patented
the time-consuming process of generating a customized
microprocessor core along with a complete software
development tool environment, producing new configurations
in a matter of hours. For more information, visit www.tensilica.com.
# # #
Editors’ Notes:
- Tensilica and Xtensa are registered trademarks
belonging to Tensilica, Inc. All other company
and product names are trademarks and/or registered
trademarks of their respective owners.
- Tensilica’s announced licensees include
Agilent, ALPS, AMCC (JNI Corporation), Astute
Networks, ATI, Avision, Bay Microsystems, Berkeley
Wireless Research Center, Broadcom, Cisco Systems,
Conexant Systems, Cypress, Crimson Microsystems,
ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson
Soft, Hughes Network Systems, Ikanos Communications,
LG Electronics, Marvell, NEC Laboratories America,
NEC Corporation, NetEffect, Neterion, Nippon
Telephone and Telegraph (NTT), NVIDIA, Olympus
Optical Co. Ltd., sci-worx, Seiko Epson, Solid
State Systems, Sony, STMicroelectronics, Stretch,
TranSwitch Corporation, and Victor Company of
Japan (JVC).
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