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May 10, 2005

Tensilica and EVE Speed SoC Development Times

Agreement Speeds Development of Complex SoCs With Multiple Xtensa Processors

Santa Clara and San Jose, Calif. -- May 10, 2005 -- Tensilica, Inc. (Santa Clara, Calif.), the only company to automate the design of optimized application-specific configurable processors for system-on-chip (SoC) design, and Emulation and Verification Engineering (EVE) (San Jose, Calif.), an innovator in advanced verification technologies, today announced an agreement that speeds the design of complex SoCs with multiple Xtensa processors.

This agreement will allow Tensilica's customers to download pre-verified register transfer level (RTL) code produced by Tensilica's Xtensa Processor Generator into EVE's hardware prototyping platform for integrated whole-chip design verification.  Tensilica's Xtensa Xplorer development environment will be linked to EVE's ZeBu hardware-based verification product to provide hardware/software co-verification and improve overall SoC simulation and debugging. The combination of EVE's automatic compiler technology for mapping SoCs to field programmable gate arrays (FPGAs) and Tensilica's Processor Generator ensures that customers will quickly be up and running with a best in class, unified hardware system debug and software validation environment.

Says Alain Raynaud, EVE's technology center director:  "The challenge of verifying huge SoC designs with multiple processors is ideally suited to our ZeBu prototyping platform. With this methodology, we significantly accelerated the development of the whole-chip hardware prototype, so engineers can spend their time designing the application and running it on the prototype at MHz speed.  It significantly reduces the need for block-level hardware verification and eliminates the pain traditionally associated with hardware emulation."

"This is an important step in SoC design," affirms Larry Przywara, director of strategic alliances for Tensilica. "While our processors are guaranteed correct by construction, they must be integrated into a highly complex SoC. By providing our users with easy access to EVE's ZeBu prototyping platform, they should be able to quickly verify their entire SOC designs."

About Emulation and Verification Engineering

EVE pioneers a new approach to hardware-assisted verification that combines the best aspects of traditional emulation and rapid prototyping systems into a single, unified environment for both ASIC/SoC debugging and embedded software validation.  It has offices in San Jose, Calif.  Telephone: (408) 881-0440.  Fax: (408) 904-5800.  It also has offices in Palaiseau, France.  Telephone: (33) 1 64532730. Fax: (33) 1 64532740.  Email:  info@eve-team.com. Web Site: http://www.eve-team.com .

About Tensilica

Tensilica was founded in July 1997 to address the growing need for optimized, application-specific microprocessor solutions in high-volume embedded applications. With a configurable and extensible microprocessor core called Xtensa, Tensilica is the only company that has automated and patented the time-consuming process of generating a customized microprocessor core along with a complete software development tool environment, producing new configurations in a matter of hours. For more information, visit www.tensilica.com .

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Editors' Notes:

  • Tensilica and Xtensa are registered trademarks belonging to Tensilica Inc. All other company and product names are trademarks and/or registered trademarks of their respective owners.
  • Tensilica's announced licensees include Agilent, ALPS, AMCC (JNI Corporation), Astute Networks, ATI, Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, Cypress, Crimson Microsystems, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, Hughes Network Systems, Ikanos Communications, LG Electronics, Marvell, NEC Laboratories America, NEC Corporation, NetEffect, Neterion, Nippon Telephone and Telegraph (NTT), NVIDIA, Olympus Optical Co. Ltd., sci-worx, Seiko Epson, Solid State Systems, Sony, STMicroelectronics, Stretch, TranSwitch Corporation, and Victor Company of Japan (JVC).
  • EVE acknowledges trademarks or registered trademarks of other organizations for their respective products and services
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“It is faster and easier to design complex SOCs using Xtensa configurable processors - especially when using the XPRES Compiler - than to hand-code complex SOC design elements in hardware using traditional RTL methods. Plus the Xtensa processors are programmable, so it will be valuable for future products and applications.”

- Katsuhiko Nishizawa, general manager of the IJP Design Department of the Imaging Products Operations Division of Seiko Epson Corporation.