Tech Support | Generator Login | Careers | Contact Us
NEWS & EVENTS

  Overview

  Press Releases

  + 2008

  + 2007

  + 2006

  + 2005

  + 2004

  + 2003

  + 2002

  + 2001

  + 2000

  + 1999

  Articles

  Events

  Presentations

  Books

  Press Room

Press Releases 2004

Tensilica’s XPRES Compiler Demo Available At Demos on Demand

Santa Clara, CA – October 14, 2004 – Tensilica, Inc. today announced that a video-based demonstration of its new XPRES Compiler is available on the Demos on Demand web site, www.demosondemand.com. Tensilica’s XPRES Compiler, picked as one of the “must see” products from DAC 2004 by Gary Smith of Gartner Dataquest, lets engineers automatically generate optimized Xtensa processors from ANSI standard C/C++ code.

Demos on Demand offers a highly sophisticated, yet easy-to-use way to show design software in action. Designers can watch display screen images of the actual software at work as Tensilica Application Engineer Michael Carchia shows how an optimized Xtensa processor is generated automatically to accelerate a target C/C++ application, which in the demonstration is a sum of absolute differences algorithm used in video compression applications.

The XPRES Compiler eliminates the need for designers to hand code their hardware using design languages like VHDL and Verilog, which take months of design and verification effort. Instead, designers input the original C/C++ algorithm that they’re trying to optimize and the XPRES Compiler, coupled with Tensilica’s automated processor generation technology, automatically generates an RTL (register transfer level) hardware description and associated software tool chain. In less than an hour, the resulting hardware block is delivered in the form of a pre-verified Xtensa LX processor core, enabling customers to future proof their designs due to its inherent programmability, and avoid the cost and risk associated with verifying custom logic. The original C code, without modification, is then compiled to run on the optimized processor. Additionally, the generated processor RTL fully rivals the performance and efficiency of hand-coded RTL blocks with many concurrent operations, efficient data types, and optimized multiple wide deep pipelines.

A direct link to Tensilica’s demo is:
http://www.demosondemand.com/dod/proddemos/vendors/pd_tensilica.aspx

About Tensilica

Tensilica was founded in July 1997 to address the growing need for optimized, application-specific microprocessor solutions in high-volume embedded applications. With a configurable and extensible microprocessor core called Xtensa, Tensilica is the only company that has automated and patented the time-consuming process of generating a customized microprocessor core along with a complete software development tool environment, producing new configurations in a matter of hours. For more information, visit www.tensilica.com.

# # #

Editors’ Notes:

  • Tensilica, and Xtensa are registered trademarks belonging to Tensilica Inc.. All other company and product names are trademarks and/or registered trademarks of their respective owners.
  • Tensilica’s announced licensees include Agilent, ALPS, AMCC (JNI Corporation), Astute Networks, Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, Cypress, Crimson Microsystems, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, Hughes Network Systems, Ikanos Communications, LG Electronics, Marvell, NEC Laboratories America, NEC Corporation, NetEffect, Nippon Telephone and Telegraph (NTT), Olympus Optical Co. Ltd., S2io, Solid State Systems, Sony, STMicroelectronics, TranSwitch Corporation, and Victor Company of Japan (JVC).
SOC book
RECOGNITION
Red herring top 100
Portable Design 2006 Editor's  Choice Award
Best Processor Cores of 2004
EDN's Hot 100 Products of 2006
QUOTABLE

“It is faster and easier to design complex SOCs using Xtensa configurable processors - especially when using the XPRES Compiler - than to hand-code complex SOC design elements in hardware using traditional RTL methods. Plus the Xtensa processors are programmable, so it will be valuable for future products and applications.”

- Katsuhiko Nishizawa, general manager of the IJP Design Department of the Imaging Products Operations Division of Seiko Epson Corporation.