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September 22, 2003

Tensilica Names Ashish Dixit Vice President of Hardware Engineering

SANTA CLARA, Calif. –September 22, 2003 – Tensilica, Inc., the leading provider of configurable and extensible processors, today announced that Ashish Dixit has been promoted to vice president of hardware engineering. Dixit reports to Beatrice Fu, senior vice president of engineering.

“Ashish has been a key member of our management team since he joined in early 1998, shortly after we started the company,” stated Chris Rowen, Tensilica president and CEO. “This promotion is a direct result of the consistent leadership he has shown directing our hardware engineering and design automation teams and pushing the architecture of our configurable processors so we continue to lead the industry in capabilities and flexibility.”

Dixit joined Tensilica in early 1998 as the director of hardware engineering. Previously he held numerous positions ranging from design engineer to director of engineering at Silicon Graphics, working on MIPS VLSI chip development. From 1983 to 1989 Dixit was a quality and reliability engineer as well as a logic design engineer at Intel Corporation. He holds a Master of Science in Computer Engineering from the University of California at Santa Barbara and a Bachelor of Science in Electrical Engineering from the Birla Institute of Technology and Science in Pilani, India. He has been issued eight patents related to configurable processors and memory management in RISC and CISC processors.

About Tensilica

Tensilica was founded in July 1997 to address the growing need for optimized, application-specific microprocessor solutions in high-volume embedded applications. With a configurable and extensible microprocessor core called Xtensa, Tensilica is the only company that has automated and patented the time-consuming process of generating a customized microprocessor core along with a complete software development tool environment, producing new configurations in a matter of hours. For more information, visit www.tensilica.com.

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Editors’ Notes:

  • “Tensilica” and “Xtensa” are registered trademarks belonging to Tensilica Inc. All other trademarks are the property of their respective holders.
  • Tensilica’s announced licensees are Agilent, Astute Networks, Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, Cypress, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, Hughes Network Systems, IC4IC, Ikanos Communications, JNI Corporation, Marvell, Mindspeed Technologies, National Semiconductor, NEC Laboratories America, NEC Corporation, Nippon Telephone and Telegraph (NTT), Olympus Optical Co. Ltd., ONEX Communications, OptiX Networks, Osaka & Kyoto Universities, S2io, Solid State System (3S), Sony, TranSwitch Corporation, Trebia Networks, Victor Company of Japan (JVC) and ZiLOG.
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“It is faster and easier to design complex SOCs using Xtensa configurable processors - especially when using the XPRES Compiler - than to hand-code complex SOC design elements in hardware using traditional RTL methods. Plus the Xtensa processors are programmable, so it will be valuable for future products and applications.”

- Katsuhiko Nishizawa, general manager of the IJP Design Department of the Imaging Products Operations Division of Seiko Epson Corporation.