Tensilica Introduces Industry’s First Integrated Development Environment for Multiple Processor SOC Hardware and Software Design

Software Development, Processor Optimization and SOC Architecture Tools Integrated Into One Common Environment

SANTA CLARA, Calif., June 16, 2003 – Tensilica, Inc. the leading supplier of configurable and extensible microprocessor cores, today introduced Xtensa Xplorer, the first integrated design environment (IDE) for SOC development that integrates software development, processor optimization and multiple-processor system-on-chip (SOC) architecture tools into one common design environment. Tensilica’s Xplorer IDE is a visual environment with a host of new automation tools that makes creating Xtensa processor-based SOC hardware and software much easier.

“Until now, IDEs have been used only for software development,” stated Bernie Rosenthal, Sr. Vice President of Sales and Marketing at Tensilica. “By extending the concept to hardware design, our customers get one integrated platform to efficiently design both the hardware and software together, make trade-offs with different processor configurations, and track projects.”

Xplorer serves as a cockpit for basic design management, invocation of Tensilica processor configuration tools (Xtensa processor generator, TIE Compiler) and software development tools. Xtensa Xplorer is particularly useful for the development of TIE (Tensilica Instruction Extension) instructions – designer-defined instruction extensions to the Xtensa processor – that maximize performance for a particular application. Different Xtensa processor and TIE configurations can be saved, profiled against the target C/C++ software, and compared. Xtensa Xplorer even includes automated graphing tools that create spreadsheet-style comparison charts of performance.

Xtensa Xplorer dramatically accelerates the processor optimization cycle by providing an automated, visual means of profiling and comparing different processor configurations. Since it only takes an hour for the Xtensa Processor Generator to create a new, customized version once the designer configures the processor and creates the instruction extensions, customers will want to try many different options. Now designers will be able to conceive of and describe new options much faster using Xtensa Xplorer.

"Xtensa Xplorer gives hardware and software engineers a common development-tool platform for designing Xtensa-based SOCs, and it raises design automation to a new level,” said Tom Halfhill, senior analyst at In-Stat/MDR. “It moves one step closer to the ideal of making embedded-system design application-centric, not hardware- or software-centric. Xtensa Xplorer also has valuable new features for designing SoCs with multiple processor cores--a trend that is sweeping the industry."

Xplorer helps bridge the hardware-software design gap for extended instructions by providing a context-sensitive TIE source code editor, a TIE-instruction-aware debugger, and a gate-count estimator. The new gate-count estimator gives real-time feedback to software designers unfamiliar with hardware development, allowing them to explore various embedded processor instruction set architectures while receiving immediate feedback on the cost implications of their extended-instruction choices.

Xplorer, while extremely useful for designs with only one Xtensa processor, is ideally targeted to multiple-processor SOC (MPSOC) designs. It facilitates MPSOC development with tools for build management; profiling; batch building; system memory map assignment; and integrated multiple-processor simulation, creation, and debugging using Tensilica’s Xtensa Modeling Protocol (XTMP).

Xplorer also provides a unified environment for:

• C/C++ application software development
• C/C++ program debugging
• Code profiling and visualization
• SOC configuration management (using multiple Xtensa processors in a system)

Three Versions of Xtensa Xplorer Offered

Standard Edition

The Xtensa Xplorer Standard Edition (Xplorer SE) features include a broad range of C/C++ code development tools and capabilities including software project management, build management, profiling and debugging.

Processor Developers Edition

The Xtensa Xplorer Processor Developers Edition (Xplorer PDE) adds advanced Xtensa processor configuration development tools to the features of the Standard Edition, including TIE editing and debugging tools and an interface to the web-based Xtensa processor generator to manage the creation of new processors.

Advanced Edition

The Xtensa Xplorer Advanced Edition (Xplorer AE) builds upon Xplorer PDE with tools that automate the creation of multiple-processor systems including building, running and debugging multiple processor simulations.

Works with Standard Software IDEs

Many of Tensilica’s customers use commercial real-time operating systems and software IDEs. Tensilica provides full support for application-optimized Xtensa configurations for operating systems and IDEs offered by Accelerated Technology (a division of Mentor Graphics), MontaVista and Wind River. Xplorer complements these IDEs by providing Xtensa specific productivity and analysis enhancements much earlier in the SOC design process.

ECLIPSE Platform

The Xtensa Xplorer IDE is based in part on the open-source ECLIPSE platform for tool integration. More information on the ECLIPSE partnership can be found at www.eclipse.org.

Pricing and Availability

The Xtensa Xplorer Standard Edition is included with no additional charge to all Xtensa-V licensees. The Xtensa Xplorer Processor Developers Edition is priced at $5,000 per user for a one-year subscription. The Xplorer Advanced Edition is an optional upgrade from the PDE version. The first pre-production release of Xtensa Xplorer will be made available in early Q3 to all active Tensilica Xtensa-V licensees. Earlier Xtensa processor licensees can get access to the Xplorer IDE by upgrading to the current version of the Tensilica software tools which also support Xtensa III and Xtensa-IV processors.

Licensed by more than 55 of the industry's leading semiconductor and systems companies, Tensilica's patented Xtensa microprocessor technology enables designers to deliver a wide variety of optimized SoCs for applications ranging from low-cost, low-power consumer electronics devices to high performance, multi-processor networking and communications systems. The Xtensa architecture provides a powerful, integrated hardware and software development environment with thousands of configuration options and an unlimited range of customer-specific extensions. Because these instructions are recognized as "native" by a complete set of software development tools, developers can simultaneously tune both application software and processor hardware to meet specific speed, power and feature goals.

About Tensilica

Tensilica was founded in July 1997 to address the growing need for optimized, application-specific microprocessor solutions in high-volume embedded applications. With a configurable and extensible microprocessor core called Xtensa, Tensilica is the only company that has automated and patented the time-consuming process of generating a customized microprocessor core along with a complete software development tool environment, producing new configurations in a matter of hours. For more information, visit www.tensilica.com.

Editors’ Notes:

• “Tensilica” and “Xtensa” are registered trademarks belonging to Tensilica Inc. All other trademarks are the property of their respective holders.
• Tensilica’s announced licensees are Agilent, Astute Networks, Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, Cypress, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hudson Soft, Hughes Network Systems, IC4IC, Ikanos Communications, JNI Corporation, Marvell, Mindspeed Technologies, National Semiconductor, NEC Networks, NEC Solutions, Nippon Telephone and Telegraph (NTT), Olympus Optical Co. Ltd., ONEX Communications, OptiX Networks, Osaka & Kyoto Universities, S2io, Sony, TranSwitch Corporation, Trebia Networks, Victor Company of Japan (JVC) and ZiLOG.