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September 30, 2002

Tensilica Licenses IBM CoreConnect Bus To Enable Xtensa Processor “Plug and Play” in IBM SOCs

Tensilica Becomes First Configurable IP Vendor to License CoreConnect Bus

 

Santa Clara, Calif., September 30, 2002 – Tensilica, Inc., the leader in configurable and extensible processors, today announced that it has become the first configurable processor IP vendor to license IBM’s CoreConnect on-chip bus architecture. Tensilica also announced the availability of an Xtensa-to-CoreConnect bus bridge in the fourth quarter of 2002. The bridge interfaces Tensilica’s configurable Xtensa processor to the IBM CoreConnect bus so customers can quickly merge multiple Xtensa processors to CoreConnect-based System-on-Chip (SOC) designs.

This announcement highlights the relationship between IBM and Tensilica, which has grown to meet the needs of their many joint customers. Tensilica was the first member of IBM’s Blue Logic IP Collaboration Program, announced March 5, 2002. Additionally, Tensilica’s Xtensa core has been proven in IBM’s Blue Logic ASIC design methodology for IBM’s SA27E 0.18-micron and advanced Cu-11 0.13-micron technologies. Tensilica and IBM have several common customer designs in volume production.

“The IBM CoreConnect bus has been very popular and widely used among SOC designers,” stated Bernie Rosenthal, senior vice president of marketing for Tensilica. “By providing customers with a configurable bridge building tool that automatically generates Xtensa to CoreConnect bridges, customers will be able to essentially ‘plug and play’ their customized Xtensa processors into CoreConnect-based SoCs.”

“As the charter member of our Blue Logic IP Collaboration Program, Tensilica is a key partner and an excellent example of the type of third-party IP that we like to make available to our customers,” said Tom Reeves, VP ASICs, IBM Microelectronics. “The configurability of the Xtensa processor makes it a natural complement to IBM’s existing IP cores portfolio. The availability of an Xtensa-to-CoreConnect bridge makes it quicker and easier for customers to design in Xtensa processors.”

Xtensa continues to be the only configurable and extensible processor with comprehensive and automatic software, modeling and EDA support. Changes made by the designer to extend the Xtensa processor hardware – adding instructions, registers, processor state and custom execution units and now the CoreConnect bus interface - are immediately and automatically reflected in the entire software tool chain, significantly reducing design complexity and time-to-market. By comparison, competitive architectures require the user to manually adjust compilers, assemblers, debuggers, operating systems, instruction set simulators, co-verification models and EDA implementation scripts when user-defined hardware changes are made to the processor RTL.

About Tensilica

Tensilica was founded in July 1997 to address the fast-growing market for configurable processors and software development tools for high volume, embedded systems. Using the company's proprietary Xtensa Processor Generator, system-on-chip (SOC) designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements in hours. Tensilica's solutions provide a proven, easy-to-use, methodology that enables designers to achieve optimum application performance in minimum design time. The Company is engaged in research, development, and customer support from its offices in Santa Clara, California; Burlington, Massachusetts; Princeton, NJ; Austin, Texas; Raleigh, NC; Oxford, U.K.; Stockholm, Sweden; Taipei, Taiwan, R.O.C.; and Yokohama, Japan. Tensilica is headquartered in Santa Clara, California (95054) at 3255-6 Scott Boulevard, and can be reached at (408) 986-8000 or via www.tensilica.com on the World Wide Web.

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Editors’ Notes:

“Tensilica” and “Xtensa” are registered trademarks belonging to Tensilica Inc. CoreConnect is a trademark of IBM. All other trademarks are the property of their respective holders.

Tensilica’s announced licensees are Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, ETRI, FUJIFILM Microdevices, Fujitsu Ltd., Hughes Network Systems, IC4IC, Ikanos Communications, JNI Corporation, Marvell (Galileo Technology), Mindspeed Technologies, National Semiconductor, NEC Networks, NEC Solutions, Nippon Telephone and Telegraph (NTT), Olympus Optical Co. Ltd., ONEX Communications, Olympus Optical, OptiX Networks, Osaka & Kyoto Universities, TranSwitch Corporation, Trebia Networks, Victor Company of Japan (JVC) and ZiLOG.

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“It is faster and easier to design complex SOCs using Xtensa configurable processors - especially when using the XPRES Compiler - than to hand-code complex SOC design elements in hardware using traditional RTL methods. Plus the Xtensa processors are programmable, so it will be valuable for future products and applications.”

- Katsuhiko Nishizawa, general manager of the IJP Design Department of the Imaging Products Operations Division of Seiko Epson Corporation.