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September 23 , 2002

ETRI Selects Tensilica for Wireless
Multimedia SOC Design

Xtensa Processor Chosen by Premier Korean Technology Center

 

Santa Clara, California, September 23, 2002 … ETRI, the Electronic and Telecommunications Research Institute, has selected Tensilica’s Xtensa configurable processor for next-generation wireless multimedia system-on-chip (SOC) design. ETRI, a non-profit government-supported technology center, is Korea’s premier SOC design resource.

“Our goal is to investigate and employ leading-edge technology that can give Korean companies a competitive advantage in the marketplace,” said Dr. Hanjin Cho, project leader of SOC design team, ETRI. “After an extensive evaluation, we picked the revolutionary Xtensa processor for our wireless multimedia SOC designs. Tensilica’s Xtensa processor allows us to add custom instructions so we can rapidly employ new features and produce designs with lower power and longer battery life.”

“The talented engineers at ETRI are determined to stay at the leading edge of wireless multimedia design,” stated Bernie Rosenthal, vice president of marketing for Tensilica. “The Xtensa processor gives them a stable base upon which they can build in features that should capture the attention of leading phone manufacturers.”

The Xtensa configurable and extensible microprocessor architecture provides a powerful, integrated hardware and software development environment with thousands of configuration options and an unlimited range of customer-specific extensions. The environment enables designers to carefully tune the processor for their particular application. With an easy-to-use graphical interface, designers can take advantage of Tensilica’s processor generator to create customized MPU solutions with specialized functional and instructions. Because these instructions are recognized as “native” by a complete set of software development tools, developers can simultaneously tune both application software and processor hardware to meet specific speed, power and feature goals.

About Tensilica

Tensilica was founded in July 1997 to address the fast-growing market for configurable processors and software development tools for high volume, embedded systems. Using the company's proprietary Xtensa Processor Generator, system-on-chip (SOC) designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements in hours. Tensilica's solutions provide a proven, easy-to-use, methodology that enables designers to achieve optimum application performance in minimum design time. The Company is engaged in research, development, and customer support from its offices in Santa Clara, California; Burlington, Massachusetts; Princeton, NJ; Austin, Texas; Raleigh, NC; Oxford, U.K.; Stockholm, Sweden; Taipei, Taiwan, R.O.C.; and Yokohama, Japan. Tensilica is headquartered in Santa Clara, California (95054) at 3255-6 Scott Boulevard, and can be reached at (408) 986-8000 or via www.tensilica.com on the World Wide Web.

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Editors Notes:

“Tensilica” and “Xtensa” are registered trademarks belonging to Tensilica Inc. Xilinx and Virtex are registered trademarks of Xilinx, Inc. All other trademarks are the property of their respective holders.

Tensilica’s announced licensees are Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, FUJIFILM Microdevices, Fujitsu Ltd., Hughes Network Systems, IC4IC, Ikanos Communications, JNI Corporation, Marvell, Mindspeed Technologies, National Semiconductor, NEC Networks, NEC Solutions, Nippon Telephone and Telegraph (NTT), Olympus Optical Co.Ltd., ONEX Communications, Olympus Optical, OptiX Networks, Osaka & Kyoto Universities, TranSwitch Corporation, Trebia Networks, Victor Company of Japan (JVC) and ZiLOG.

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“It is faster and easier to design complex SOCs using Xtensa configurable processors - especially when using the XPRES Compiler - than to hand-code complex SOC design elements in hardware using traditional RTL methods. Plus the Xtensa processors are programmable, so it will be valuable for future products and applications.”

- Katsuhiko Nishizawa, general manager of the IJP Design Department of the Imaging Products Operations Division of Seiko Epson Corporation.