Bay Microsystems Uses Xtensa Processor Architecture To Reach New Heights in 10G Integration and Packet Processing Performance

Tensilica's Xtensa Core Enables Industry's First Single-Chip 0C192/10G Network Processor/Traffic Manager

July 29, 2002, Santa Clara, CA. - Tensilica, Inc., the configurable and extensible microprocessor pioneer, today announced that Bay Microsystems has used its Xtensa architecture to develop the Montego Internetworking Processor, a programmable network processor (NPU) that integrates packet processing and traffic management (TM) at OC192c/10G for the first time on a single chip.

"With its ease of configuration and flexible development tool suite, Tensilica's Xtensa core is the ideal complement to our own programmable pipelined processing elements," said Chuck Gershman, founder and senior vice president of Bay Microsystems, Inc. "We optimized Xtensa's configurable RISC based instruction set for use within Montego's exception/control plane in order to provide our OEM customers with a simple to use, high performance processor."

"Embedded designers need a flexible processor development environment that enables them to break through the limitations of traditional approaches, while significantly reducing time-to-market," said Bernie Rosenthal, senior vice president of marketing at Tensilica. "With Xtensa, companies like Bay Microsystems finally have the tools they need to deliver truly innovative embedded processors that power the next generation of SOCs."

Bay Microsystems' Montego NPU/TM addresses a broad range of carrier-class applications such as access concentrators; voice, wireless and xDSL gateways; multi-service switches and routers; cable head ends and intelligent optical transport equipment. The company employs a deterministic, superscalar architecture that achieves sustainable packet processing of 31.25 million packets per second regardless of traffic patterns or network services, while supporting data throughput of 16 Gbps. Determinism enables the devices to achieve sustained line rate performance at minimum packet size.

Xtensa is Tensilica's proven configurable and extensible microprocessor architecture that provides a powerful, integrated hardware and software development environment with thousands of configuration options and an unlimited range of customer-specific extensions. The environment enables designers to carefully tune the processor for specific functionality. With an easy-to-use graphical interface, designers can take advantage of Tensilica's processor generator to create customized MPU solutions with specialized functions and instructions. Because these instructions are recognized as "native" by a complete set of software development tools, developers can simultaneously tune both application software and processor hardware to meet specific speed, power and feature goals.

About Bay Microsystems

Bay Microsystems Inc. is a privately held, fabless communication IC company. Bay's Internetworking Processor™ (InP) Family of programmable packet processing devices combines scalability, intelligence processing and ultra-high performance in highly integrated solutions. The InP Family includes Montego™, the industry's first single chip highly integrated OC192c/10G Network Processor and Traffic Manager with switching. Bay's highly experienced management and world-class engineering team have three generations of proven expertise in architecture, implementation, deployment, marketing and management of network processors. For more information visit the website at www.baymicrosystems.com.

About Tensilica

Tensilica was founded in July 1997 to address the fast-growing market for configurable processors and software development tools for high volume, embedded systems. Using the company's proprietary Xtensa processor generator, system-on-chip (SOC) designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements in hours. Tensilica's solutions provide a proven, easy-to-use, methodology that enables designers to achieve optimum application performance in minimum design time. The company is engaged in research, development, and customer support from its offices in Santa Clara, California; Burlington, Massachusetts; Princeton, NJ; Austin, Texas; Raleigh, NC; Oxford, U.K.; Stockholm, Sweden; Taipei, Taiwan, R.O.C.; and Yokohama, Japan. Tensilica is headquartered in Santa Clara, California (95054) at 3255-6 Scott Boulevard, and can be reached at (408) 986-8000 or via www.tensilica.com on the World Wide Web.

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Editors Notes:

“Tensilica” and “Xtensa” are registered trademarks belonging to Tensilica Inc. Xilinx and Virtex are registered trademarks of Xilinx, Inc. All other trademarks are the property of their respective holders.

Tensilica’s announced licensees are Avision, Bay Microsystems, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, FUJIFILM Microdevices, Fujitsu Ltd., Hughes Network Systems, IC4IC, Ikanos Communications, JNI Corporation, Marvell, Mindspeed Technologies, National Semiconductor, NEC Networks, NEC Solutions, Nippon Telephone and Telegraph (NTT), Olympus Optical Co.Ltd., ONEX Communications, Olympus Optical, OptiX Networks, Osaka & Kyoto Universities, TranSwitch Corporation, Trebia Networks, Victor Company of Japan (JVC) and ZiLOG.