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January 28, 2002

Tensilica Awarded Key Patent for Microprocessors in SOC Applications

Santa Clara, Calif., January 28, 2002. Tensilica Inc., the privately-held configurable and extensible microprocessor pioneer, today announced that it had been granted U.S. Patent Number 6,282,633 for a “High Data Density RISC processor.” The patent covers a wide variety of new RISC processor architecture methods, especially those for high-volume, low-cost applications where code density and performance are both critical.

The patent covers fundamental inventions including the use of large register files with highly packed instructions (less than 32 bits in length), dense encoding of multiple operations per instruction, and use of mode-less variable length RISC instructions to reduce code size and power and increase performance. All these techniques are employed in Tensilica’s Xtensa® processor family, and may also prove valuable for other high-density processor architectures.

According to Chris Rowen Ph.D., Tensilica’s president and CEO, “This is one of our most significant patent actions to date because of the patent’s scope and the central importance of protecting our fundamental architecture innovation. We have seen other leading processor innovators struggle to fend off clone-makers because their patents cover only obscure or unimportant features. We didn’t want to leave any open doors, and this very broad patent on high-density RISC instruction sets does exactly that.”

About Tensilica, Inc.

Tensilica was founded in July 1997 to address the fast-growing market for configurable processors and software development tools for high volume, embedded systems. Using the company's proprietary Xtensa Processor Generator, system-on-chip (SOC) designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements in hours. Tensilica's solutions provide a proven, easy-to-use, methodology that enables designers to achieve optimum application performance in minimum design time. The Company is engaged in research, development, and customer support from its offices in Santa Clara, California; Burlington, Massachusetts; Princeton, NJ; Raleigh, NC; Austin, Texas; Oxford, U.K.; Stockholm, Sweden; Taipei, Taiwan, R.O.C.; and Yokohama, Japan. Tensilica is headquartered in Santa Clara, California (95054) at 3255-6 Scott Boulevard, and can be reached at (408) 986-8000 or via www.tensilica.com on the World Wide Web.

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Editors’ Notes:

“Tensilica” and "Xtensa" are registered trademarks belonging to Tensilica Inc. All other registered trademarks or trademarks are property of their respective owners.

Tensilica's announced licensees are Avision, Berkeley Wireless Research Center, Broadcom, Cisco Systems, Conexant Systems, FUJIFILM Microdevices, Fujitsu Ltd., Hughes Network Systems, Ikanos Communications, JNI Corporation, Marvell (Galileo Technology), Mindspeed Technologies, National Semiconductor, NEC Networks, NEC Solutions, Nippon Telephone and Telegraph (NTT), ONEX Communications, Osaka & Kyoto Universities, TranSwitch Corporation, Victor Company of Japan (JVC) and ZiLOG.

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“It is faster and easier to design complex SOCs using Xtensa configurable processors - especially when using the XPRES Compiler - than to hand-code complex SOC design elements in hardware using traditional RTL methods. Plus the Xtensa processors are programmable, so it will be valuable for future products and applications.”

- Katsuhiko Nishizawa, general manager of the IJP Design Department of the Imaging Products Operations Division of Seiko Epson Corporation.