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May 22, 2000

Tensilica to Unveil Xtensa III Technology, New Options at Embedded Processor Forum


SANTA CLARA, Calif. ---May 22, 2000 --- Tensilica Inc., the Santa Clara-based provider of application-specific processor technology, announced today that Chris Rowen, president and CEO will announce and detail Xtensa(TM) III, the latest version of the company's unique processor core architecture and intellectual property suite at MicroDesign Resources' "Embedded Processor Forum," in San Jose, California on June 14, 2000.

Besides enhancements to the Tensilica Instruction Extension (TIE) language that allows definition of new data types and creation of associated memory access, arithmetic, field manipulation and Boolean instructions that operate on those data types, Xtensa III also includes powerful new preconfigured coprocessor options including a SIMD DSP and a 32-bit Floating Point.

Rowen said that, "The Embedded Processor Forum is the premiere venue for disclosure of major embedded processor innovations. We are looking forward to describing important innovations in Xtensa processor generation, including high-performance enhancements for signal and image processing, key embedded software, and significant additions to the Tensilica Instruction Extension (TIE) Compiler."

About Tensilica

Tensilica was founded in July 1997 to address the fast-growing market for application-specific microprocessor cores and software development tools for high volume, embedded systems. Using the company's proprietary Xtensa™ Processor Generator, system-on-a-chip (SOC) designers can develop a processor subsystem hardware design and a complete software development tool environment tailored to their specific requirements in hours.

Tensilica's solutions provide a proven, easy-to-use, methodology that enables designers to achieve optimum application performance in minimum design time. The Company is engaged in research, development, and customer support from its offices in Santa Clara, California, Waltham, Massachusetts, Princeton, N.J., Houston, Texas, Reading, U.K. and Yokohama, Japan.

Tensilica is headquartered in Santa Clara, California (95054) at 3255-6 Scott Boulevard, and can be reached at (408) 986-8000 or via www.tensilica.com on the World Wide Web.

"Tensilica", "Xtensa" and "OSKit" are the trademarks belonging to Tensilica Inc.

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“It is faster and easier to design complex SOCs using Xtensa configurable processors - especially when using the XPRES Compiler - than to hand-code complex SOC design elements in hardware using traditional RTL methods. Plus the Xtensa processors are programmable, so it will be valuable for future products and applications.”

- Katsuhiko Nishizawa, general manager of the IJP Design Department of the Imaging Products Operations Division of Seiko Epson Corporation.